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Arm Cortex‑A76 Core Technical Reference Manual : VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2

VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2

The VDISR_EL2 records that a virtual SError interrupt has been consumed by an ESB instruction executed at Non-secure EL1.

Bit field descriptions

VDISR_EL2 is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.

Configurations

See VDISR_EL2 at EL1 using AArch64.

Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

This section contains the following subsection:

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