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Arm Cortex‑A76 Core Technical Reference Manual : MVFR2_EL1, Media and VFP Feature Register 2, EL1

MVFR2_EL1, Media and VFP Feature Register 2, EL1

The MVFR2_EL1 describes the features provided by the AArch64 Advanced SIMD and floating-point implementation.

Bit field descriptions

MVFR2_EL1 is a 32-bit register.

Figure B5-5 MVFR2_EL1 bit assignments


[31:8]
RES0Reserved.
FPMisc, [7:4]

Indicates support for miscellaneous floating-point features.

0x4

Supports:

  • Floating-point selection.
  • Floating-point Conversion to Integer with Directed Rounding modes.
  • Floating-point Round to Integral Floating-point.
  • Floating-point MaxNum and MinNum.
SIMDMisc, [3:0]

Indicates support for miscellaneous Advanced SIMD features.

0x3

Supports:

  • Floating-point Conversion to Integer with Directed Rounding modes.
  • Floating-point Round to Integral Floating-point.
  • Floating-point MaxNum and MinNum.
Configurations
There are no configuration notes.

Usage constraints

Accessing the MVFR2_EL1

To access the MVFR2_EL1:

MRS <Xt>, MVFR2_EL1 ; Read MVFR2_EL1 into Xt

Register access is encoded as follows:

Table B5-6 MVFR2_EL1 access encoding

op0 op1 CRn CRm op2
11 000 0000 0011 010
Accessibility
This register is accessible as follows:
EL0 EL1(NS) EL1(S) EL2 EL3 (SCR.NS = 1) EL3(SCR.NS = 0)
- RO RO RO RO RO
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