You copied the Doc URL to your clipboard.

Arm Cortex‑A76 Core Technical Reference Manual : ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register

ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register

ERR0PFGCDNR is the Cortex®‑A76 node register that generates one of the errors that are enabled in the corresponding ERR0PFGCTL register.

Bit field descriptions

ERR0PFGCDNR is a 32-bit register and is RW.

Figure B3-5 ERR0PFGCDNR bit assignments


CDN, [31:0]
Count Down value. The reset value of the Error Generation Counter is used for the countdown.
Configurations

There are no configuration options.

ERR0PFGCDNR resets to UNKNOWN.

When ERRSELR.SEL==0, ERR0PFGCDNR is accessible from ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1.

Was this page helpful? Yes No