You copied the Doc URL to your clipboard.

Arm Cortex‑A76 Core Technical Reference Manual : ERR0STATUS, Error Record Primary Status Register

ERR0STATUS, Error Record Primary Status Register

The ERR0STATUS contains information about the error record:

  • Whether any error has been detected.
  • Whether any detected error was not corrected and returned to a master.
  • Whether any detected error was not corrected and deferred.
  • Whether a second error of the same type was detected before software handled the first error.
  • Whether any error has been reported.
  • Whether the other error record registers contain valid information.

Bit field descriptions

ERR0STATUS is a 32-bit register.

Figure B3-8 ERR0STATUS bit assignments


AV, [31]

Address Valid. The possible values are:

0ERR0ADDR is not valid.
1

ERR0ADDR contains an address associated with the highest priority error recorded by this record.

V, [30]

Status Register valid. The possible values are:

0ERR0STATUS is not valid.
1ERR0STATUS is valid. At least one error has been recorded.
UE, [29]
Uncorrected error. The possible values are:
0

No error that could not be corrected or deferred has been detected.

1At least one error that could not be corrected or deferred has been detected. If error recovery interrupts are enabled, then the interrupt signal is asserted until this bit is cleared.
ER, [28]
Error reported. The possible values are:
0No external abort has been reported.
1The node has reported an external abort to the master that is in access or making a transaction.
OF, [27]
Overflow. The possible values are:
0
  • If UE == 1, then no error status for an Uncorrected error has been discarded.
  • If UE == 0 and DE == 1, then no error status for a Deferred error has been discarded.
  • If UE == 0, DE == 0, and CE !== 0b00, then:

    The corrected error counter has not overflowed.

1More than one error has occurred and so details of the other error have been discarded.
MV, [26]
Miscellaneous Registers Valid. The possible values are:
0

ERR0MISC0 and ERR0MISC1 are not valid.

1This bit indicates that ERR0MISC0 contains additional information about any error that is recorded by this record.
CE, [25:24]
Corrected error. The possible values are:
0b00No corrected error recorded.
0b10At least one corrected error recorded.
DE, [23]
Deferred error. The possible values are:
0No errors were deferred.
1At least one error was not corrected and deferred by poisoning.
PN, [22]

Poison. The value is:

0

The Cortex®‑A76 core cannot distinguish a poisoned value from a corrupted value.

UET, [21:20]
Uncorrected Error Type. The value is:
0b00Uncontainable.
[19:5]
RES0.
Reserved.
SERR, [4:0]
Primary error code. The possible values are:
0x0No error.
0x1Errors due to fault injection.
0x2ECC error from internal data buffer.
0x6ECC error on cache data RAM.
0x7ECC error on cache tag or dirty RAM.
0x8Parity error on TLB data RAM.
0x12

Error response for a cache copyback.

0x15

Deferred error from slave not supported at the consumer. For example, poisoned data received from a slave by a master that cannot defer the error further.

Configurations

There are no configuration notes.

ERR0STATUS resets to 0x00000000.

ERR0STATUS is accessible from the following registers when ERRSELR.SEL==0:

Was this page helpful? Yes No