Error system register summary
The ERR0* registers are agnostic to the architectural state. For example, this means that for ERRSELR==0 and ERRSELR_EL1==0, ERXPFGFR and ERXPFGFR_EL1 will both access ERR0PFGFR.
For those registers not described in this chapter, see the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.
The following table describes the architectural error record registers.
Table B3-1 Architectural error system register summary
The following table describes the error record registers that are IMPLEMENTATION DEFINED.
|Register mnemonic||Size||Register name||Access aliases from AArch64|
|ERR0PFGCDNR||32||ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register||ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1|
|ERR0PFGCTLR||32||ERR0PFGCTLR, Error Pseudo Fault Generation Control Register||ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1|
|ERR0PFGFR||32||ERR0PFGFR, Error Pseudo Fault Generation Feature Register||ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1|