ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
ICC_CTLR_EL1 controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented.
Bit field descriptions
ICC_CTLR_EL1 is a 32-bit register and is part of:
- The GIC system registers functional group.
- The GIC control registers functional group.
Figure B4-3 ICC_CTLR_EL1 bit assignments
- RES0, [31:16]
- A3V, 
Affinity 3 Valid. The value is:
The CPU interface logic supports non-zero values of Affinity 3 in SGI generation System registers.
- SEIS, 
SEI Support. The value is:
The CPU interface logic does not support local generation of SEIs.
- IDbits, [13:11]
Identifier bits. The value is:
The number of physical interrupt identifier bits supported is 16 bits.
This field is an alias of ICC_CTLR_EL3.IDbits.
- PRIbits, [10:8]
Priority bits. The value is:
The core supports 32 levels of physical priority with 5 priority bits.
- RES0, 
- PMHE, 
Priority Mask Hint Enable. This bit is read only and is an alias of ICC_CTLR_EL3.PMHE. The possible values are:
Disables use of ICC_PMR as a hint for interrupt distribution.
Enables use of ICC_PMR as a hint for interrupt distribution.
- RES0, [5:2]
- EOImode, 
- End of interrupt mode for the current security state. The possible values
ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality. Accesses to ICC_DIR are UNPREDICTABLE.
ICC_EOIR0 and ICC_EOIR1 provide priority drop functionality only. ICC_DIR provides interrupt deactivation functionality.
- CBPR, 
- Common Binary Point Register. Control whether the same register is used for
interrupt preemption of both Group 0 and Group 1 interrupt. The possible
ICC_BPR0 determines the preemption group for Group 0 interrupts.
ICC_BPR1 determines the preemption group for Group 1 interrupts.
ICC_BPR0 determines the preemption group for Group 0 and Group 1 interrupts.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.