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Arm Cortex‑A76 Core Technical Reference Manual : ICC_CTLR_EL3, Interrupt Controller Control Register, EL3

ICC_CTLR_EL3, Interrupt Controller Control Register, EL3

ICC_CTLR_EL3 controls aspects of the behavior of the GIC CPU interface and provides information about the features implemented.

Bit field descriptions

ICC_CTLR_EL3 is a 32-bit register and is part of:

  • The GIC system registers functional group.
  • The Security registers functional group.
  • The GIC control registers functional group.

Figure B4-4 ICC_CTLR_EL3 bit assignments


RES0, [31:18]
Reserved, RES0.
nDS, [17]

Disable Security not supported. Read-only and writes are ignored. The value is:

1

The CPU interface logic does not support disabling of security, and requires that security is not disabled.

RES0, [16]
Reserved, RES0.
A3V, [15]

Affinity 3 Valid. This bit is RAO/WI.

SEIS, [14]

SEI Support. The value is:

0

The CPU interface logic does not support generation of SEIs.

IDbits, [13:11]

Identifier bits. The value is:

0x0The number of physical interrupt identifier bits supported is 16 bits.

This field is an alias of ICC_CTLR_EL3.IDbits.

PRIbits, [10:8]

Priority bits. The value is:

0x4The core supports 32 levels of physical priority with 5 priority bits. Accesses to ICC_AP0R{1—3} and ICC_AP1R{1—3} are UNDEFINED.
RES0, [7]
Reserved, RES0.
PMHE, [6]

Priority Mask Hint Enable. The possible values are:

0Disables use of ICC_PMR as a hint for interrupt distribution.
1Enables use of ICC_PMR as a hint for interrupt distribution.
RM, [5]

Routing Modifier. This bit is RAZ/WI.

EOImode_EL1NS, [4]

EOI mode for interrupts handled at Non-secure EL1 and EL2.

Controls whether a write to an End of Interrupt register also deactivates the interrupt.

EOImode_EL1S, [3]

EOI mode for interrupts handled at Secure EL1.

Controls whether a write to an End of Interrupt register also deactivates the interrupt.

EOImode_EL3, [2]

EOI mode for interrupts handled at EL3.

Controls whether a write to an End of Interrupt register also deactivates the interrupt.

CBPR_EL1NS, [1]

Common Binary Point Register, EL1 Non-secure.

Control whether the same register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1 and EL2.

CBPR_EL1S, [0]

Common Binary Point Register, EL1 Secure.

Control whether the same register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupt at EL1.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.

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