ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1
ICC_SRE_EL1 controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL0 and EL1.
Bit field descriptions
ICC_SRE_EL1 is a 32-bit register and is part of:
- The GIC system registers functional group.
- The GIC control registers functional group.
Figure B4-5 ICC_SRE_EL1 bit assignments
- RES0, [31:3]
- DIB, 
Disable IRQ bypass. The possible values are:
IRQ bypass enabled.
IRQ bypass disabled.
This bit is an alias of ICC_SRE_EL3.DIB
- DFB, 
Disable FIQ bypass. The possible values are:
FIQ bypass enabled.
FIQ bypass disabled.
This bit is an alias of ICC_SRE_EL3.DFB
- SRE, 
System Register Enable. The value is:
The System register interface for the current Security state is enabled.
This bit is RAO/WI. The core only supports a system register interface to the GIC CPU interface.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.