ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3
ICC_SRE_EL3 controls whether the System register interface or the memory-mapped interface to the GIC CPU interface is used for EL3.
Bit field descriptions
ICC_SRE_EL3 is a 32-bit register and is part of:
- The GIC system registers functional group.
- The Security registers functional group.
- The GIC control registers functional group.
Figure B4-7 ICC_SRE_EL3 bit assignments
- RES0, [31:4]
- Enable, 
Enables lower Exception level access to ICC_SRE_EL1 and ICC_SRE_EL2. The value is:
- Secure EL1 accesses to Secure ICC_SRE_EL1 do not trap to EL3.
- EL2 accesses to Non-secure ICC_SRE_EL1 and ICC_SRE_EL2 do not trap to EL3.
- Non-secure EL1 accesses to ICC_SRE_EL1 do not trap to EL3.
This bit is RAO/WI.
- DIB, 
Disable IRQ bypass. The possible values are:
IRQ bypass enabled.
IRQ bypass disabled.
- DFB, 
Disable FIQ bypass. The possible values are:
FIQ bypass enabled.
FIQ bypass disabled.
- SRE, 
System Register Enable. The value is:
The System register interface for the current Security state is enabled.
This bit is RAO/WI. The core only supports a system register interface to the GIC CPU interface.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Generic Interrupt Controller Architecture Specification.