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In a standalone configuration, the core consists of up to four cores and a DSU that connects the cores to an external memory system.

For more information about the DSU, see the Arm® DynamIQ™ Shared Unit Technical Reference Manual.

The main components of the Cortex®‑A76 core are:

  • Instruction fetch.
  • Instruction decode.
  • Register rename.
  • Instruction issue.
  • Execution pipelines.
  • L1 data memory system.
  • L2 memory system.

The following figure is an overview of the Cortex‑A76 core.

Figure A2-1 Cortex‑A76 core overview


There are multiple asynchronous bridges between the Cortex‑A76 core and the DSU. Only the CPU bridge between the Cortex‑A76 core and the DSU can be configured to run synchronously, however it does not affect the other interfaces such as debug, trace, and GIC which are always asynchronous. For more information on how to set the CPU bridge to run either synchronously or asynchronously, see Configuration Guidelines in the Arm® DynamIQ™ Shared Unit Configuration and Sign-off Guide.
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