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AFSR1_EL3, Auxiliary Fault Status Register 1, EL3

AFSR1_EL3 provides additional IMPLEMENTATION DEFINED fault status information for exceptions that are taken to EL3. This register is not used in the Cortex®‑A76 core.

Bit field descriptions

AFSR1_EL3 is a 32-bit register, and is part of:

  • The Exception and fault handling registers functional group.
  • The Security registers functional group.
  • The IMPLEMENTATION DEFINED functional group.

Figure B2-9 AFSR1_EL3 bit assignments


RES0, [31:0]
Reserved, RES0.
Configurations

There are no configuration notes.

Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.

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