CPUACTLR3_EL1, CPU Auxiliary Control Register 3, EL1
The CPUACTLR3_EL1 provides IMPLEMENTATION DEFINED configuration and control options for the core.
Bit field descriptions
CPUACTLR3_EL1 is a 64-bit register, and is part of the implementation defined registers functional group.
Figure B2-21 CPUACTLR3_EL1 bit assignments
- Reserved, [63:0]
- Reserved for Arm® internal use.
CPUACTLR3_EL1 is common to the Secure and Non-secure states.
- Accessing the CPUACTLR3_EL1
The CPUACTLR3_EL1 can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled.
Setting many of these bits can cause significantly lower performance on your code. Therefore, Arm strongly recommends that you do not modify this register unless directed by Arm.
This register can be read using MRS with the following syntax:
This register can be written using MSR with the following syntax:
MSR <systemreg>, <Xt>
This syntax is encoded with the following settings in the instruction encoding:
This register is accessible in software as follows:
'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.
- Traps and enables
For a description of the prioritization of any generated exceptions, see Exception priority order in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch64 state, and see Synchronous exception prioritization for exceptions taken to AArch64 state.
Write access to this register from EL1 or EL2 depends on the value of bit of ACTLR_EL2 and ACTLR_EL3.