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CPUECTLR_EL1, CPU Extended Control Register, EL1

The CPUECTLR_EL1 provides additional IMPLEMENTATION DEFINED configuration and control options for the core.

Bit field descriptions

CPUECTLR_EL1 is a 64-bit register, and is part of the 64-bit registers functional group.

This register resets to value 0x0000000961563000.

Figure B2-23 CPUECTLR_EL1 bit assignments


RES0, [63:62]
res0Reserved.
MXP_EN, [61]

Max-power throttle enable. The possible values are:

0Disables max-power throttling mechanism. This is the reset value.
1Enables max-power throttling mechanism.

Note

Both the MXP_EN bit and the MPMMEN input pin at the DSU cluster level must be asserted to enable the max-power throttling mechanism.
RES0, [60:59]
res0Reserved.
MXP_TP, [58:57]

Percentage of throttling in the Load-Store and Vector Execute units during the period when throttling has been triggered and is active. The possible values are:

00Throttle by 60%. This is the reset value.
01Throttle by 50%.
10Throttle by 40%.
11Throttle by 30%.
MXP_ATHR, [56:55]

Peak activity threshold at which max-power throttling is triggered. The possible values are:

00Max-power throttling triggered at 70% of peak activity. This is the reset value.
01Max-power throttling triggered at 60% of peak activity.
10Max-power throttling triggered at 50% of peak activity.
11Max-power throttling triggered at 40% of peak activity.
MM_VMID_THR, [54]

VMID filter threshold. The possible values are:

0Flush VMID filter after 16 unique VMID allocations to the MMU Translation Cache. This is the reset value.
1Flush VMID filter after 32 unique VMID allocations to the MMU Translation Cache.
MM_ASP_EN, [53]

Disables allocation of splintered pages in L2 TLB. The possible values are:

0Enables allocation of splintered pages in the L2 TLB. This is the reset value.
1Disables allocation of splintered pages in the L2 TLB.
MM_CH_DIS, [52]

Disables use of contiguous hint. The possible values are:

0Enables use of contiguous hint. This is the reset value.
1Disables use of contiguous hint.
MM_TLBPF_DIS, [51]

Disables L2 TLB prefetcher. The possible values are:

0Enables L2 TLB prefetcher. This is the reset value.
1Disables L2 TLB prefetcher.
HPA_MODE, [50:49]

Hardware Page Aggregation (HPA) mode. The possible values are:

00Moderately conservative hardware page aggregation. This is the reset value.
01Aggressive hardware page aggregation.
10Moderately aggressive hardware page aggregation.
11Conservative hardware page aggregation.
HPA_CAP, [48]

Limited or full hardware page aggregation selection . The possible values are:

0Limited hardware page aggregation. This is the reset value.
1Full hardware page aggregation.
HPA_L1_DIS, [47]

Disables HPA in L1 TLBs (but continues to use HPA in L2 TLB). The possible values are:

0Enables hardware page aggregation in L1 TLBs. This is the reset value.
1Disables hardware page aggregation in L1 TLBs.
HPA_DIS, [46]

Disables hardware page aggregation. The possible values are:

0Enables hardware page aggregation. This is the reset value.
1Disables hardware page aggregation.
RES0, [45:44]
res0Reserved.
L2_FLUSH, [43]

Allocation behavior of copybacks caused by L2 cache hardware flush and DC CISW instructions targeting the L2 cache. If it is known that data is likely to be used soon by another core, setting this bit can improve system performance. The possible values are:

0L2 cache flushes and invalidates by set/way do not allocate in the L3 cache. Cache lines in the UniqueDirty state cause WriteBack transactions with the allocation hint cleared, while cache lines in UniqueClean or SharedClean states cause address-only Evict transactions. This is the reset value.
1 L2 cache flushes by set/way allocate in the L3 cache. Cache lines in the UniqueDirty or UniqueClean state cause WriteBackFull or WriteEvictFull transactions, respectively, both with the allocation hint set. Cache lines in the SharedClean state cause address-only Evict transactions.
RES0, [42]
res0Reserved.
PFT_MM, [41:40]

DRAM prefetch using PrefetchTgt transactions for table walk requests. The possible values are:

00Disable prefetchtgt generation for requests from the Memory Management unit (MMU). This is the reset value.
01Conservatively generate prefetchtgt for cacheable requests from the MMU, always generate for non-cacheable.
10Aggressively generate prefetchtgt for cacheable requests from the MMU, always generate for non-cacheable.
11Always generate prefetchtgt for cacheable requests from the MMU, always generate for non-cacheable.
PFT_LS, [39:38]

DRAM prefetch using PrefetchTgt transactions for load and store requests. The possible values are:

00Disable prefetchtgt generation for requests from the Load-Store unit (LS). This is the reset value.
01Conservatively generate prefetchtgt for cacheable requests from the LS, always generate for non-cacheable.
10Aggressively generate prefetchtgt for cacheable requests from the LS, always generate for non-cacheable.
11Always generate prefetchtgt for cacheable requests from the LS, always generate for non-cacheable.
PFT_IF, [37:36]

DRAM prefetch using PrefetchTgt transactions for instruction fetch requests. The possible values are:

00Disable prefetchtgt generation for requests from the Instruction Fetch unit (IF). This is the reset value.
01Conservatively generate prefetchtgt for cacheable requests from the IF, always generate for non-cacheable.
10Aggressively generate prefetchtgt for cacheable requests from the IF, always generate for non-cacheable.
11Always generate prefetchtgt for cacheable requests from the IF, always generate for non-cacheable.
CA_UCLEAN_EVICT_EN, [35]

Enables sending WriteEvict transactions on the CPU CHI interface for UniqueClean evictions. WriteEvict transactions update downstream caches. Enable WriteEvict transactions only if there is an additional level of cache below the CPU's Level 2 cache. The possible values are:

0 Disables sending data with UniqueClean evictions.
1Enables sending data with UniqueClean evictions. This is the reset value.
CA_EVICT_DIS, [34]

Disables sending of Evict transactions on the CPU CHI interface for clean cache lines that are evicted from the core. Evict transactions are required only if the system contains a snoop filter that requires notification when the core evicts the cache line. The possible values are:

0 Enables sending Evict transactions. This is the reset value.
1Disables sending Evict transactions.
RES0, [33]
res0Reserved.
ATOMIC_ACQ_NEAR, [32]

An atomic instruction to WB memory with acquire semantics that does not hit in the cache in Exclusive state, may make up to one fill request. The possible values are:

0 Acquire-atomic is near if cache line is already Exclusive, otherwise make far atomic request.
1Acquire-atomic will make up to 1 fill request to perform near. This is the reset value.
ATOMIC_ST_NEAR, [31]

A store atomic instruction to WB memory that does not hit in the cache in Exclusive state, may make up to one fill request. The possible values are:

0 Store-atomic is near if cache line is already Exclusive, otherwise make far atomic request. This is the reset value.
1Store-atomic will make up to 1 fill request to perform near.
ATOMIC_REL_NEAR, [30]

An atomic instruction to WB memory with release semantics that does not hit in the cache in Exclusive state, may make up to one fill request. The possible values are:

0 Release-atomic is near if cache line is already Exclusive, otherwise make far atomic request.
1Release-atomic will make up to 1 fill request to perform near. This is the reset value.
ATOMIC_LD_NEAR, [29]

A load atomic (including SWP and CAS) instruction to WB memory that does not hit in the cache in Exclusive state, may make up to one fill request. The possible values are:

0 Load-atomic is near if cache line is already Exclusive, otherwise make far atomic request.
1Load-atomic will make up to 1 fill request to perform near. This is the reset value.
TLD_PRED_DIS, [28]

Disables Transient Load Prediction. The possible values are:

0 Enables transient load prediction. This is the reset value.
1Disables transient load prediction.
RES0, [27]
res0Reserved.
DTLB_CABT_EN , [26]

Enables TLB Conflict Data Abort Exception. The possible values are:

0 Disables TLB conflict data abort exception. This is the reset value.
1Enables TLB conflict data abort exception.
WS_THR_L2, [25:24]

Threshold for direct stream to L2 cache on store. The possible values are:

00256B.
014KB. This is the reset value.
108KB.
11Disables direct stream to L2 cache on store.
WS_THR_L3, [23:22]

Threshold for direct stream to L3 cache on store. The possible values are:

00768B.
0116KB. This is the reset value.
1032KB.
11Disables direct stream to L3 cache on store.
WS_THR_L4, [21:20]

Threshold for direct stream to L4 cache on store. The possible values are:

0016KB.
0164KB. This is the reset value.
10128KB.
11Disables direct stream to L4 cache on store.
WS_THR_DRAM, [19:18]

Threshold for direct stream to DRAM on store. The possible values are:

0064KB.
011MB, for memory designated as outer-allocate. This is the reset value.
101MB, allocating irrespective of outer-allocation designation.
11Disables direct stream to DRAM on store.
WS_THR_DCZVA, [17]

Have DCZVA use a lower WS_THR_L2 configuration. The possible values are:

0 DCZVA behaves like normal store wrt WS_THR_L2.
1DCZVA will use one lower stream threshold from WS_THR_L2. This is the reset value.
RES0, [16]
res0Reserved.
PF_DIS, [15]

Disables data-side hardware prefetching. The possible values are:

0Enables hardware prefetching. This is the reset value.
1Disables hardware prefetching.
RES0, [14]
res0Reserved.
PF_SS_L2_DIST, [13:12]

Single cache line stride prefetching L2 distance. The possible values are:

0022
0128
1034
1140. This is the reset value.
RES0, [11:10]
res0Reserved.
RES0, [9]
res0Reserved.
PF_STI_DIS, [8]

Disables store prefetches at issue (not overridden by CPUECTLR_EL1[15]). The possible values are:

0

Enables store prefetching. This is the reset value.

1

Disables store prefetching.

PF_STS_DIS, [7]

Disables store-stride prefetches. The possible values are:

0

Enables store prefetching. This is the reset value.

1

Disables store prefetching.

RES0, [6]
res0Reserved.
RPF_DIS, [5]

Disables region prefetcher. The possible values are:

0

Enables region prefetching. This is the reset value.

1

Disables region prefetching.

RPF_LO_CONF, [4]

Region prefetcher training behavior. The possible values are:

0

Limited training for region prefetcher on single accesses. This is the reset value.

1

Always train the region prefetcher on single accesses, which results in fewer prefetch requests.

RPF_PHIT_EN, [3]

Enable region prefetcher propagation on hit. The possible values are:

0

Disables region prefetcher propagation on hit. This is the reset value.

1

Enables region prefetcher propagation on hit.

RES0, [2:1]
res0

Reserved.

EXTLLC, [0]
Internal or external Last-level cache (LLC) in the system. The possible values are:
0

Indicates that an internal Last-level cache is present in the system, and that the DataSource field on the master CHI interface indicates when data is returned from the LLC. This is used to control how the LL_CACHE* PMU events count. This is the reset value.

1

Indicates that an external Last-level cache is present in the system, and that the DataSource field on the master CHI interface indicates when data is returned from the LLC. This is used to control how the LL_CACHE* PMU events count.

Configurations

This register has no configuration options.

Usage constraints

Accessing the CPUECTLR_EL1

The CPU Extended Control Register can be written only when the system is idle. Arm recommends that you write to this register after a powerup reset, before the MMU is enabled.

This register can be read using MRS with the following syntax:

MRS <Xt>,<systemreg>

This register can be written using MSR with the following syntax:

MSR <systemreg>, <Xt>

This syntax is encoded with the following settings in the instruction encoding:

<systemreg> op0 op1 CRn CRm op2
CPUECTLR_EL1 11 000 1111 0001 100
Accessibility

This register is accessible in software as follows:

<systemreg> Control Accessibility
E2H TGE NS EL0 EL1 EL2 EL3
CPUECTLR_EL1 x x 0 - RW n/a RW
CPUECTLR_EL1 x 0 1 - RW RW RW
CPUECTLR_EL1 x 1 1 - n/a RW RW

'n/a' Not accessible. The PE cannot be executing at this Exception level, so this access is not possible.

Traps and enables

For a description of the prioritization of any generated exceptions, see Synchronous exception prioritization in the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for exceptions taken to AArch64 state.

Access to this register depends on bit[1] of ACTLR_EL2 and ACTLR_EL3.

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