ERRSELR_EL1, Error Record Select Register, EL1
The ERRSELR_EL1 selects which error record should be accessed through the Error Record system registers. This register is not reset on a warm reset.
Bit field descriptions
ERRSELR_EL1 is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.
Figure B2-34 ERRSELR_EL1 bit assignments
- RES0, [63:1]
- SEL, 
- Selects which error record should be accessed.
Select record 0 containing errors from Level 1 and Level 2 RAMs located on the Cortex®‑A76 core.
Select record 1 containing errors from Level 3 RAMs located on the DSU.
There are no configuration notes.
Bit fields and details not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.