ESR_EL3, Exception Syndrome Register, EL3
The ESR_EL3 holds syndrome information for an exception taken to EL3.
Bit field descriptions
ESR_EL3 is a 32-bit register, and is part of the Exception and fault handling registers functional group.
Figure B2-37 ESR_EL3 bit assignments
- EC, [31:26]
- Exception Class. Indicates the reason for the exception that this register holds information about.
- IL, [25]
-
Instruction Length for synchronous exceptions. The possible values are:
0
16-bit. 1
32-bit. This field is
1
for the SError interrupt, instruction aborts, misaligned PC, Stack pointer misalignment, data aborts for which the ISV bit is0
, exceptions caused by an illegal instruction set state, and exceptions using the0x0
Exception Class. - ISS, [24:0]
-
Syndrome information.
When reporting a virtual SEI, bits[24:0] take the value of VSESRL_EL2[24:0].
When reporting a physical SEI, the following occurs:
- IDS==0 (architectural syndrome).
- AET always reports an uncontainable error (UC) with value
0b000
or an unrecoverable error (UEU) with value0b001
. - EA is RES0.
When reporting a synchronous data abort, EA is RES0.
See VSESR_EL2, Virtual SError Exception Syndrome Register.
- Configurations
-
RW fields in this register reset to architecturally unknown values.