ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1
The ID_AA64MMFR2_EL1 provides information about the implemented memory model and memory management support in the AArch64 Execution state.
Bit field descriptions
ID_AA64MMFR2_EL1 is a 64-bit register, and is part of the Identification registers functional group.
This register is Read Only.
Figure B2-45 ID_AA64MMFR2_EL1 bit assignments
- RES0, [63:16]
- IESB, [15:12]
Indicates whether an implicit Error Synchronization Barrier has been inserted. The value is:
- LSM, [11:8]
Indicates whether LDM and STM ordering control bits are supported. The value is:
LSMAOE and nTLSMD bit not supported.
- UAO, [7:4]
Indicates the presence of the User Access Override (UAO). The value is:
UAO is supported.
- CnP, [3:0]
Common not Private. Indicates whether a TLB entry is pointed at a translation table base register that is a member of a common set. The value is:
CnP bit is supported.
There are no configuration notes.
Bit fields and details that are not provided in this description are architecturally defined. See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile.