ERR0FR, Error Record Feature Register
The ERR0FR defines which of the common architecturally defined features are implemented and, of the implemented features, which are software programmable.
Bit field descriptions
ERR0FR is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.
The register is Read Only.
Figure B3-3 ERR0FR bit assignments
- CEO, [19:18]
Corrected Error Overwrite. The value is:
Counts CE if a counter is implemented and keeps the previous error status. If the counter overflows, ERR0STATUS.OF is set to 1.
- DUI, [17:16]
Error recovery interrupt for deferred errors. The value is:
The core does not support this feature.
- RP, 
Repeat counter. The value is:
A first repeat counter and a second other counter are implemented. The repeat counter is the same size as the primary error counter.
- CEC, [14:12]
- Corrected Error Counter. The value is:
The node implements an 8-bit standard CE counter in ERR0MISC0[39:32].
- CFI, [11:10]
- Fault handling interrupt for corrected errors. The value
The node implements a control for enabling fault handling interrupts on corrected errors.
- UE, [9:8]
- In-band uncorrected error reporting. The value is:
The node implements in-band uncorrected error reporting, that is external aborts.
- FI, [7:6]
- Fault handling interrupt. The value is:
The node implements a fault handling interrupt and implements controls for enabling and disabling.
- UI, [5:4]
- Error recovery interrupt for uncorrected errors. The value is:
The node implements an error recovery interrupt and implements controls for enabling and disabling.
- ED, [1:0]
- Error detection and correction. The value is:
The node implements controls for enabling or disabling error detection and correction.
- ERR0FR resets to
- ERR0FR is accessible from the following registers when ERRSELR.SEL==0: