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Configuring MMU accesses

By programming the IRGN and ORGN bits, you can configure the MMU to perform translation table walks in cacheable or non-cacheable regions:

AArch64Appropriate TCR_ELx register.

If the encoding of both the ORGN and IRGN bits is Write-Back, the data cache lookup is performed and data is read from the data cache. External memory is accessed, if the ORGN and IRGN bit contain different attributes, or if the encoding of the ORGN and IRGN bits is Write-Through or Non-cacheable.

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