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Mis-programming contiguous hints

In the case of a mis-programming contiguous hint, when there is a descriptor that contains a set CH bit, all contiguous VAs contained in this block should be included in the input VA address space that is defined for stage 1 by TxSZ for TTBx or for stage 2 by {SL0, T0SZ}.

The Cortex®‑A76 core treats such a block as not causing a translation fault.

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