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TLB match process

The Armv8-A architecture provides support for multiple maps from the VA space that are translated differently.

TLB entries store the context information required to facilitate a match and avoid the need for a TLB flush on a context or virtual machine switch.

Each TLB entry contains a:

  • VA.
  • PA.
  • Set of memory properties that include type and access permissions.

Each entry is either associated with a particular ASID or global. In addition, each TLB entry contains a field to store the VMID in the entry applicable to accesses from Non-secure EL0 and EL1 Exception levels.

Each entry is associated with a particular translation regime.

  • EL3 in Secure state in AArch64 state only.
  • EL2 or EL0 in Non-secure state.
  • EL1 or EL0 in Secure state.
  • EL1 or EL0 in Non-secure state.

A TLB match entry occurs when the following conditions are met:

  • Its VA, moderated by the page size such as the VA bits[48:N], where N is log2 of the block size for that translation that is stored in the TLB entry, matches the requested address.
  • Entry translation regime matches the current translation regime.
  • The ASID matches the current ASID held in the CONTEXTIDR, TTBR0, or TTBR1 register, or the entry is marked global.
  • The VMID matches the current VMID held in the VTTBR_EL2 register.
  • The ASID and VMID matches are ignored when ASID and VMID are not relevant.

    ASID is relevant when the translation regime is:

    • EL2 in Non-secure state with HCR_EL2.E2H and HCR_EL2.TGE set to 1.
    • EL1 or EL0 in Secure state.
    • EL1 or EL0 in Non-secure state.

    VMID is relevant for EL1 or EL0 in Non-secure state.

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