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Power up and down sequences

The following approach allows taking the Cortex®‑A76 cores in the cluster in and out of coherence.

Core powerdown

To take a core out of coherence ready for core powerdown, the following power down steps must be performed:

  1. Save all architectural states.
  2. Configure the GIC distributor to disable or reroute interrupts away from this core.
  3. Set the CPUPWRCTLR.CORE_PWRDN_EN bit to 1 to indicate to the power controller that a powerdown is requested.
  4. Execute an ISB instruction.
  5. Execute a WFI instruction.

All L1 and L2 cache disabling, L1 and L2 cache flushing, and communication with the L3 memory system is performed in hardware after the WFI is executed, under the direction of the power controller.

Note

Executing any WFI instruction when the CPUPWRCTLR.CORE_PWRDN_EN bit is set automatically masks out all interrupts and wake-up events in the core. If executed when the CPUPWRCTLR.CORE_PWRDN_EN bit is set the WFI never wakes up and the core needs to be reset to restart.

For information about cluster powerdown, see the Arm® DynamIQ™ Shared Unit Technical Reference Manual.

Core powerup

To bring a core into coherence after reset, no software steps are required.

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