Cache protection behavior
The configuration of the RAS extension that is implemented in the Cortex®‑A76 core includes cache protection.
In this case, the Cortex‑A76 core protects against errors that result in a RAM bitcell holding the incorrect value.
The RAMs in the Cortex‑A76 core have the following capability:
- Single Error Detect. One bit of parity is applicable to the entire word. The word size is specific for each RAM and depends on the protection granule.
- Interleaved parity
- One bit of parity is applicable to the even bits of the word, and one bit of parity is applicable to the odd bits of the word.
- Single Error Correct, Double Error Detect.
Table A8-1 Cache protection behavior indicates which protection type is applied to each RAM.
The core can progress and remain functionally correct when there is a single bit error in any RAM.
If there are multiple single bit errors in different RAMs, or within different protection granules within the same RAM, then the core also remains functionally correct.
If there is a double bit error in a single RAM within the same protection granule, then the behavior depends on the RAM:
- For RAMs with SECDED capability, the core detects and either reports or defers the error. If the error is in a cache line containing dirty data, then that data might be lost.
- For RAMs with only SED, the core does not detect a double bit error. This might cause data corruption.
If there are three or more bit errors within the same protection granule, then depending on the RAM and the position of the errors within the RAM, the core might or might not detect the errors.
The cache protection feature of the core has a minimal performance impact when no errors are present.
Table A8-1 Cache protection behavior
|RAM||Protection type||Protection granule||Correction behavior|
|L1 instruction cache tag||1 parity bit||31 bits||The line that contains the error is invalidated from the L1 instruction cache and fetched again from the subsequent memory system.|
|L1 instruction cache data||SED||72 bits||The line that contains the error is invalidated from the L1 instruction cache and fetched again from the subsequent memory system.|
|L1 data cache tag||SECDED||34 bits + 7 bits for ECC attached to the word.||The cache line that contains the error gets evicted, corrected in line, and refilled to the core.|
|L1 data cache data||SECDED||32 bits of data +1 poison bit + 7 bits for ECC attached to the word.||The cache line that contains the error gets evicted, corrected in line, and refilled to the core.|
|L1 Prefetch History Table (PHT)||None||-||-|
|MMU translation cache||2 interleaved parity bits||67 bits||Entry invalidated, new pagewalk started to refetch it.|
|MMU replacement policy||None||-|
|MMU biased replacement||None||-|
|L2 cache tag||
128KB L2 - 7 ECC bits for 38 tag bits
256KB L2 - 7 ECC bits for 37 tag bits
512KB L2 - 7 ECC bits for 36 tag bits
|Tag is corrected inline.|
|L2 cache data||
|8 ECC bits for 64 data bits||Data is corrected inline.|
|L2 TQ data||SECDED||8 ECC bits for 64 data bits||Data is corrected inline.|
To ensure that progress is guaranteed even in case of hard error, the core returns corrected data to the core, and no cache access is required after data correction.