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The System Control Register

The System Control Register (SCTLR) is a register that controls standard memory, system facilities and provides status information for functions that are implemented in the core.

cpsr_bits.png

Not all bits are available above EL1. The individual bits represent the following:

UCI

When this is set, EL0 access for DC CVAU, DC CIVAC, DC CVAC, and IC IVAU instructions is enabled in AArch64.

EE

Exception endianness.

0     Little endian

1     Big endian.

EOE

Endianness of data accesses at EL0. The possible values of this bit are:

0   Little-endian.

1     Big-endian.

WXN

Write permission implies XN (eXecute Never)

0     Regions with write permission are not forced to XN.

1     Regions with write permission are forced to XN.

nTWE

A value of 0 means that WFE instructions are trapped to EL1 if the instruction would have caused the core to sleep.

A value of 1 means that WFE instructions are executed as normal.

nTWI

A value of 0 means that WFI instructions are trapped to EL1 if the instruction would have caused the core to sleep.

A value of 1 means that WFI instructions are executed as normal.

UCT

A value of 1 means EL0 access to the CTR_EL0 register in AArch64 is enabled.

A value of 0 mean EL0 access to the CLR_ELO register in AArch64 is disabled.

DZE

Access to DC ZVA instruction at EL0.

0      Execution not allowed.

1      Execution allowed.

I

This is an enable bit for instruction caches at EL0 and EL1.

0     Instruction accesses to Normal memory are not cached.

1     Instruction accesses to Normal memory are cached.

UMA

User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64.

0      Attempts to use an MSR or MSR instruction to access the DAIF is trapped at EL1.

1  Attempt to use an MSR or MRS instruction to access the DAIF is not trapped at EL1.

SED

Disables SETEND instructions at EL0 using AArch32.

0     SETEND instructions are enabled.

1     The SETEND instruction is disabled.

ITD

IT Disable bit. The possible values of this bit are:

0     The IT instruction is available.

1     The IT instruction is treated as a 16-bit instruction. Only another 16-bit instruction, or the first half of a 32-bit instruction, can follow. This depends on the implementation.

CP15BEN

CP15 barrier enable. If implemented, it is an enable bit for the AArch32 CP15 DMB, DSB, and ISB barrier operations.

SA0

Stack Alignment Check Enable for EL0.

SA

Stack Alignment Check Enable.

C

Data cache enable. This is an enable bit for data caches at EL0 and EL1. Data accesses to Cacheable Normal memory are cached.

A

Alignment check enable bit.

M

Enable the MMU.

Accessing the SCTLR

To access the SCTLR_ELn, use:

MRS <Xt>, SCTLR_ELn 			// Read SCTLR_ELn into Xt 
MSR SCTLR_ELn, <Xt> 			// Write Xt to SCTLR_ELn

As in the following example:

MRS X0, SCTLR_EL1		   // Read System Control Register configuration 
					// data
ORR X0, X0, #(1 << 2)	     // Set [C] bit (bit [2]) to enable data caching
ORR X0, X0, #(1 << 12)	    // Set [I] bit (bit [12]) to enable instruction 
					// caching 
MSR SCTLR_EL1, X0		   // Write System Control Register configuration 
					// data

Note

Caches in the processor must be invalidated before data and instruction caches are enabled in any of the Exception levels.

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