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Processor state in exception handling

The current state of the processor is stored within separate PSTATE fields. If an exception is taken, the PSTATE information is saved in the Saved Program Status Register (SPSR_ELn) which exists as SPSR_EL3, SPSR_EL2, and SPSR_EL1.

At AArch64:

exceptions_from_aarch64.png

At AArch32:

exceptions_from_aarch32.png

When an exception is taken, the core state is saved from PSTATE in the SPSR at the Exception level the exception is taken to. For example, if the core takes an exception to EL1, the core state is saved in SPSR_EL1.

The following table shows the PSTATE fields:

Name

Description

Notes

N

Negative condition flag.

 

Z

Zero condition flag.

 

C

Carry condition flag.

 

V

oVerflow condition flag.

 

D

Debug mask bit.

AArch64 only

A

SError mask bit.

 

I

IRQ mask bit.

 

F

FIQ mask bit.

 

SS

Software Step bit.

 

IL

Illegal Execution state bit.

 

EL (2)

Exception level.

 

nRW

Execution state.

0 = 64-bit

1 = 32-bit

 

SP

Stack pointer selector.

0 = SP_EL0

1 = SP_ELn

AArch64 only

Q

Cumulative saturation (sticky) flag.

AArch32 only

GE (4)

Greater than or Equal flags.

AArch32 only

IT (8)

If-Then execution bits.

AArch32 only

J

J bit.

AArch32 only

T

T32 bit.

AArch32 only

E

Endianness bit.

AArch32 only

M

Mode field.

AArch32 only

The exception bit mask bits (DAIF) allow the exception events to be masked. The exception is not taken when the bit is set.

D
Debug exceptions mask.
A
SError interrupt Process state mask, for example, asynchronous external abort.
I
IRQ interrupt Process state mask.
F
FIQ interrupt Process state mask.

The SP field selects whether the current Exception level stack pointer or SP_EL0 is used. This can be done at any Exception level, except EL0.

The IL field, when set, causes execution of the next instruction to trigger an exception. It is used in illegal execution returns, for example, trying to return to EL2 as AArch64 when it is configured for AArch32.

The Software Stepping (SS) bit is used by debuggers to execute a single instruction and then take a debug exception on the following instruction.

PSTATE fields are accessed using special-purpose registers. The Special-purpose registers are read directly using MRS instruction, and written directly using MSR (register) instructions.

The special registers are:

CurrentEL

Holds the current Exception level.

DAIF

Specifies the current interrupt mask bits.

NZCV

Holds the condition flags

SPSel

At EL1 or higher, this selects between the SP for the current Exception level and SP_EL0

Some of these separate fields, such as CurrentEL, DAIF, and NZCV, are copied into a compact form in SPSR_ELn when taking an exception (and the other way around when returning).

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