You copied the Doc URL to your clipboard.

Running an application on an FVP with varying vector width

This describes running a simple program that has been compiled using Arm® Compiler 6. It shows how you can increase the SVE vector width on the FVP model to reduce the total number of executed instructions.

This example uses a project, sve_array_sum, that is provided with DS-5, which you can import. The application contains two vectorizable loops. The first loop fills the array, values, with floating-point values. The second loop adds all these values together.

Procedure

  1. In the Project Explorer view, select the project sve_array_sum. If the project does not contain the compiled .axf file, then right-click the project and build it using Arm Compiler 6.
  2. DS-5 provides an FVP debug configuration for this project, sve_array_sum_FVP. To open the debug configuration, right-click the project and select Debug As > Debug Configurations and select sve_array_sum_FVP from the list of DS-5 Debugger configurations.
  3. In the Model parameters field, specify these three options:
    • -C bp.secure_memory=false
    • -C SVE.ScalableVectorExtension.veclen=2
    • --stat

    The veclen option defines the SVE vector width, in units of 64-bit (8-byte) blocks. The maximum value of veclen is 32, which corresponds to the architectural maximum SVE vector width of 2048-bit (256-byte) blocks. The SVE architecture only supports vector lengths in 128-bit (16 byte) blocks, so all values of veclen must be even. For example, a veclen value of 8 signifies 512-bit vector width SVE registers.

    The --stat option prints statistics about the application when the FVP model exits.

    Figure 4-12 Model parameters for vector length 128 bits (veclen=2)

    Model parameters for vector length 128 bits (veclen=2)

  4. Click Apply and then click Debug to load the application on the FVP model.
  5. To see the SVE registers, open the Registers view from the main menu Windows > Show View. If the SVE registers are not visible, in Register set, select All registers and then expand AARCH64 > SVE > Data.

    When veclen is set to 2, the SVE Z registers are 128-bit registers.

    Figure 4-13 SVE registers with vector length 128 bits (veclen=2)

    SVE registers with vector length 128 bits (veclen=2)

  6. Using the Debug Control view, you can step through the application or run it till a breakpoint is hit. You can open the Debug Control view using Window > Show View.
  7. Using the Debug Control view, run the application to completion. Then right-click the connection and select Disconnect from Target to disconnect from the model.
  8. Open the Target Console view from the main menu Window > Show View.

    Figure 4-14 Target console with vector length 128 bits (veclen=2)

    Target console with vector length 128 bits (veclen=2)

    Note

    The statistics output shows Total instructions executed: 8897. This number might be different depending on the other compiler settings.
  9. To change the vector width for the FVP model, open the debug configurations for the project. In the Model parameters, change the veclen parameter to 32. Then click Debug.

    Figure 4-15 Model parameters for vector length 2048 bits (veclen=32)

    Model parameters for vector length 2048 bits (veclen=32)

  10. Go to the Registers view and note that the SVE Z registers are 2048-bit registers when veclen is 32.

    Figure 4-16 SVE registers with vector length 2048 bits (veclen=32)

    SVE registers with vector length 2048 bits (veclen=32)

  11. Run the application to completion and then disconnect from the target. In the Target Console view, see that the total instructions executed is lower. The wider the SVE vector, the fewer instructions are needed to process the array.

    Figure 4-17 Target console with vector length 2048 bits (veclen=32)

    Target console with vector length 2048 bits (veclen=32)

Was this page helpful? Yes No