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DMC520 component

This section describes the DMC520 component

DMC520 - about

This LISA+ component is a model of the ARM® CoreLink™ DMC-520 Dynamic Memory Controller.

A platform can have multiple instances of this component. For example:

        //LISA instantiation
        composition
        {
            // Memory controllers
            dmc520_0            : DMC520("passthrough_debug_access"=true);
            dmc520_1            : DMC520("passthrough_debug_access"=true);
        }

Limitations:

  • The model does not support address striping.
  • It works with linear addresses and not in rank,bank,row,column form.
  • It does not include any mechanism for error injection or detection.
  • Scrubbing functionality is only provided from the interface point of view.
  • It does not implement direct read or write commands.
  • It does not implement any performance counters.

The DMC-520 model has different interfaces to those in the hardware due to the level of abstraction of memory in Fast Models. These are the differences:

  • Like the hardware, the model has a slave port for configuring register accesses, abp_pvbus_s, and an AXI interface for incoming memory transactions that are attempting to access memory that is managed by the DMC.

  • The DMC-520 hardware component translates incoming transactions on the AXI interface to a format that is conducive to accessing DRAM chips. The model performs TrustZone™ access control and models the DMC readiness state, but does not translate the transactions. If allowed, the model forwards incoming transactions to be handled by a memory storage handling component that works at the transaction level.

DMC520 - ports

This section describes the ports.

Table 4-58 DMC520 - ports

Name Protocol Type Description
all_or_interrupt_signal master Signal A combined interrupt that is the logical OR of the other interrupts.
apb_pvbus_s slave PVBus Slave port for configuring register accesses.
arch_fsm_interrupt_signal master Signal The DMC has detected a change in the architectural state.
failed_access_interrupt_signal master Signal The DMC has detected a system request that has failed a permissions check and a previously detected assertion was not cleared.
filter_pvbus_m master PVBus Memory transaction output to filter units.
filter_pvbus_s slave PVBus Memory transaction input from filter units.
reset_signal slave Signal Reset signal input.
scrub_event_in[8] slave Signal Scrub event n trigger.
scrub_event_out[8] slave Signal Scrub event n triggered.

DMC520 - parameters

This section describes the parameters.

Table 4-59 DMC520 - parameters

Name Type Allowed values Default value Description
override_default_config bool true or false false Override default block-all behavior of DMC. Allow access to memory.
passthrough_debug_access bool true or false false Always allow debug access to memory.

DMC520 - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies.

DMC520 - trace sources

This section describes the trace sources for the DMC520 model.

DMC520_ArchStateUpdate

Fields:

CMD enum
Command received to process.
CURRENT_STATE enum
State before the command processed.
NEW_STATE enum
Final state after command processed.
SUCCESS bool
Whether succeeded or failed.
DMC_AccessInResetState

DMC Register access in reset state.

DMC_AccessToUnimplementedRegister

Fields:

ADDR unsigned int
Address of the accessed register.
READ bool
Transaction type is read or write.
DMC_BlockingTransactions

Fields:

ADDR unsigned int
Address for the transaction.
MASTER_ID unsigned int
Which master initiated the transaction.
NS bool
Whether the transaction is secure or non-secure.
READ bool
Transaction type is read or write.
DMC_CheckPermissions

Fields:

ADDR unsigned int
Transaction address.
MASTER_ID unsigned int
Which master initiated the transaction.
NS bool
Whether the transaction is secure or non-secure.
OUTSIDE_DEFAULT bool
Whether the access failed due to outside default region.
READ bool
Transaction type is read or write.
SUCCESS bool
Whether transaction succeeded or failed.
TZ_FAIL bool
Whether the access failed due to invalid permissions.
DMC_ReadToWriteOnlyRegister

Fields:

ADDR unsigned int
Address of the accessed register.
DMC_RegRead

Fields:

REG_NAME string
The name of the register read.
REG_OFFSET unsigned int
The address of the register read.
VALUE unsigned int
Read Value from the register.
DMC_RegWrite

Fields:

REG_NAME string
The name of the register updated.
REG_OFFSET unsigned int
The address of the register updated.
UPDATED_VALUE unsigned int
New Value in the register.
VALUE unsigned int
Old Value in the register.
DMC_WriteToReadOnlyRegister

Fields:

ADDR unsigned int
Address of the accessed register.

DMC520 - verification and testing

DMC-520 has been extensively used as part of the FVPs that are used for system-level testing of ARM subsystems.

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