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ICS307 component

This section describes the ICS307 component.

ICS307 - about

This LISA+ component is a model of an ICS307 clock divider. You can use it to convert the rate of one ClockSignal to another ClockSignal by application of configurable multiplier, divider and scale values.

The Divider ratio can be set by startup parameters or at runtime by a configuration port. Changes to the input ClockSignal rate and divider ratio are reflected immediately by the output ClockSignal ports.

Three values determine the divisor ratio:

  • vdw.
  • rdw.
  • od.

To calculate the divisor ratio, use:

Divisor = ((rdw+2) * scale) / (2 * (vdw+8))

where scale is derived from this table indexed by od:

Table 4-94 od to scale conversion

od scale
0 10
1 2
2 8
3 4
4 5
5 7
6 3
7 6

The default values of vdw, rdw and od are 4, 6 and 3 to give a default divisor rate of:

((6+2) * 4) / (2 * (4+8)) = 4/3

ICS307 - ports

This section describes the ports.

Table 4-95 ICS307 ports

Name Protocol Type Description
clk_in ClockSignal Slave Master clock rate
clk_out_clk1 ClockSignal Master Modified clock rate
clk_out_ref ClockSignal Master Pass through of master clock rate for divider chaining
configuration ICS307Configuration Slave Configuration port for setting divider ratio dynamically

ICS307 - parameters

This section describes the parameters.

Table 4-96 ICS307 parameters

Name Type Allowed values Default value Description
vdw Integer 0-255 4 Used to calculate clock divider ratio
rdr Integer 0-255 6 Used to calculate clock divider ratio
od Integer 0-7 3 Used to calculate clock divider ratio

ICS307 - verification and testing

This component passes tests as part of the VE example system by using VE test suites and by booting operating systems.

ICS307 - performance

ARM® expects this component to have little effect on the performance of PV systems. However, modifying the ICS307 timing parameters is relatively slow, so ARM recommends you do so rarely.

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