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PL041_AACI component

This section describes the PL041_AACI component.

PL041_AACI - about

This LISA+ component is a model of a PL041 Advanced Audio CODEC Interface (AACI).

This component also contains a minimal register model of the LM4529 secondary codec as implemented on development boards supplied by ARM.

This component is not a complete implementation of the AACI because the following functionality is not implemented:

  • Audio input.
  • DMA access to FIFOs, rather than Programmed I/O.
  • Programming of the secondary codec through FIFOs rather than slot registers.

The PL041_AACI component is designed to connect to an audio output component such as AudioOutFile or AudioOut_SDL.

PL041_AACI - ports

This section describes the ports.

Table 4-130 PL041_AACI ports

Name Protocol Type Description
clk_ref_in ClockSignal Slave Reference clock input, typically 25MHz
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
audio AudioControl Master Used to communicate with an audio out device
irq Signal Master Single IRQ output port

PL041_AACI - registers

This section describes the registers.

Table 4-131 PL041_AACI registers

Name Offset Access Description
RXCR1 0x00 Read/write FIFO1 receive control
TXCR1 0x04 Read/write FIFO1 transmit control
SR1 0x08 Read/write Channel 1 status
ISR1 0x0C Read/write Channel 1 interrupt status
IE1 0x10 Read/write Channel 1 interrupt enable
RXCR2 0x14 Read/write FIFO2 receive control
TXCR2 0x18 Read/write FIFO2 transmit control
SR2 0x1C Read/write Channel 2 status
ISR2 0x20 Read/write Channel 2 interrupt status
IE2 0x24 Read/write Channel 2 interrupt enable
RXCR3 0x28 Read/write FIFO3 receive control
TXCR3 0x2C Read/write FIFO3 transmit control
SR3 0x30 Read/write Channel 3 status
ISR3 0x34 Read/write Channel 3 interrupt status
IE3 0x38 Read/write Channel 3 interrupt enable
RXCR4 0x3C Read/write FIFO4 receive control
TXCR4 0x40 Read/write FIFO4 transmit control
SR4 0x44 Read/write Channel 4 status
ISR4 0x48 Read/write Channel 4 interrupt status
IE4 0x4C Read/write Channel 4 interrupt enable
SL1RX 0x50 Read/write Slot 1 receive data
SL1TX 0x54 Read/write Slot 1 transmit data
SL2RX 0x58 Read/write Slot 2 receive data
SL2TX 0x5C Read/write Slot 2 transmit data
SL12RX 0x60 Read/write Slot 12 receive data
SL12TX 0x64 Read/write Slot 12 transmit data
LSFR 0x68 Read/write Slot flag register
SLISTAT 0x6C Read/write Slot interrupt status
SLIEN 0x70 Read/write Slot interrupt enable
ALLINTCLR 0x74 Write only All interrupts clear
MAINCR 0x78 Read/write Main control
RESET 0x7C Read/write Reset control
SYNC 0x80 Read/write Sync control
ALLINTS 0x84 Read/write All FIFO interrupts status
MAINFR 0x88 Read/write Main flags register

PL041_AACI - verification and testing

This component passes tests using the ALSA driver for this component under Linux.

PL041_AACI - performance

This component relies on a timed callback from the simulation so might have a small impact on simulation performance.

The ability to play audio through this component depends on the AudioOut Component in use and on the performance requirements of the software running on the simulated system. The rate of FIFO draining is controlled by the audio output to which the component is connected. This might not correspond to the rate that would be expected from the reference clock.

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