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PL111_CLCD component
This section describes the PL111_CLCD component.
PL111_CLCD - about
This LISA+ component is a model of the PL110 CLCD, and also implements the hardware cursor of the PL111_CLCD (ARM PrimeCell Color LCD Controller (PL111)), which is the major change compared with PL110.
PL111_CLCD - ports
This section describes the ports.
Table 4-142 PL111_CLCD ports
Name | Protocol | Type | Description |
---|---|---|---|
pvbus |
PVBus | Slave | Slave port for connection to PV bus master/decoder |
intr |
Signal | Master | Interrupt signaling for flyback events |
clk_in |
ClockSignal | Slave | Master clock input, typically 24MHz, to drive pixel clock timing |
display |
LCD | Master | Connection to visualization component |
control |
Value | Slave | Auxiliary control register 1 |
pvbus_m |
PVBus | Master | DMA port for video data |
Related reference
PL111_CLCD - parameters
This section describes the parameters.
Table 4-143 PL111_CLCD parameters
Name | Type | Allowed values | Default value | Description |
---|---|---|---|---|
pixel_double_limit |
int |
- | 300,
|
Threshold in horizontal pixels, below which pixels sent to the framebuffer are doubled in size horizontally and vertically. |
PL111_CLCD - registers
This section describes the registers.
Table 4-144 PL111_CLCD registers
Name | Offset | Access | Description |
---|---|---|---|
LCDTiming0 |
|
Read/write | Horizontal timing |
LCDTiming1 |
|
Read/write | Vertical timing |
LCDTiming2 |
|
Read/write | Clock and polarity control |
LCDTiming3 |
|
Read/write | Line end control |
LCDUPBASE |
|
Read/write | Upper panel frame base address |
LCDLPBASE |
|
Read/write | Lower panel frame base address |
LCDControl |
|
Read/write | Control |
LCDIMSC |
|
Read/write | Interrupt mask |
LCDRIS |
|
Read only | Raw interrupt status |
LCDMIS |
|
Read only | Masked interrupt status |
LCDICR |
|
Write only | Interrupt clear |
LCDIPCURR |
|
Read only | Upper panel current address |
LCDLPCURR |
|
Read only | Lower panel current address |
LCDPalette | 0x200 - |
Read/write | Palette registers |
CursorImage | 0x800- |
Read/write | Cursor image RAM register |
ClcdCrsCtrl |
|
Read/write | Cursor control |
ClcdCrsrConfig |
|
Read/write | Cursor configuration |
ClcdCrsrPalette0 |
|
Read/write | Cursor palette |
ClcdCrsrPalette1 |
|
Read/write | Cursor palette |
ClcdCrsrXY | 0XC10 |
Read/write | Cursor XY position |
ClcdCrsrClip |
|
Read/write | Cursor clip position |
ClcdCrsrIMSC |
|
Read/write | Cursor interrupt mask set/clear |
ClcdCrsrICR |
|
Read/write | Cursor interrupt clear |
ClcdCrsrRIS |
|
Read/write | Cursor raw interrupt status |
ClcdCrsrMIS |
|
Read/write | Cursor masked interrupt status |
CLCDPeriphID0 |
|
Read | Peripheral ID register |
CLCDPeriphID1 |
|
Read | Peripheral ID register |
CLCDPeriphID2 |
|
Read | Peripheral ID register |
CLCDPeriphID3 |
|
Read | Peripheral ID register |
CLCDPCellID0 |
|
Read | PrimeCell ID register |
CLCDPCellID1 |
|
Read | PrimeCell ID register |
CLCDPCellID2 |
|
Read | PrimeCell ID register |
CLCDPCellID3 |
|
Read | PrimeCell ID register |
PL111_CLCD - verification and testing
This component passes tests as part of the PL111 test system using PL11x test suites.