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TZC_400 component

This section describes the TZC_400 component.

TZC_400 - about

This LISA+ component is a model of r0p1 of the ARM® TZC-400 CoreLink™ TZC-400 TrustZone® Address Space Controller.

The TZC-400 determines, under software control, whether a particular bus master is permitted to issue Non-secure accesses to a particular physical address.

The component has:

  • Eight address regions in addition to the base region, region 0.
  • A programmable control block for security-access permissions configuration through the Advanced Peripheral Bus (APB).
  • Up to four address filters that share common set region set-up registers.
  • Software configurable permission check failure reporting and interrupt signaling.
  • Filtering with a Non-Secure Access ID (NSAID).
  • A gate keeper, to allow or block accesses to the filter unit.
  • Configurable reset values of region configuration registers and other key configuration registers.

Unlike the hardware, it does not have:

  • Asynchronous clocks. The model does not need clocks for data transfer, or clock signals.
  • QoS Virtual Network (QVN) support. Specifically, it does not implement the vnet bits[27:24] in FAIL_ID_<x> registers.
  • Fast Path and Fast Path ID. In the model, transactions occur at similar speeds.
  • 256 outstanding accesses globally for each read or write Normal Paths and configurable 8, 16, or 32 outstanding accesses on Fast Path read access. The model does not support QVN, and this concept is meaningless for a PV level model.
  • Configurable address bus width, data bus width, transaction ID tag, and USER bus width. A single bus implementation, PVBus, covers these AXI bus hardware implementation details.

TZC_400 - ports

This section describes the ports.

Table 4-193 TZC_400 ports

Name Protocol Type Description
master tzcint Signal Master TrustZone interrupt signal, controlled by ACTION register
slave tzc_reset Signal Slave Reset signal from external master
apbslave_s Signal Slave Bus access for control register
filter_pvbus_s[4] PVBus Slave Incoming bus traffic to filter units
filter_pvbus_m[4] PVBus Master Outgoing bus traffic from filter units

TZC_400 - parameters

This section describes the parameters.

Table 4-194 TZC_400 parameters

Name Type Allowed values Default value Description
diagnostics int 0x0-0x4 0x0 Level of diagnostics messages in the model.
id_mappinga int - -b Maps from the low-order 16 bits of the Master ID into an NSAID value that the system designer specifies.c Deprecated: ARM recommends master_id_from_label.
master_id_from_labela int - false Take Master IDs directly from the label field in PVBus transactions, and from them draw NSAIDs directly without mapping. When true, this parameter overrides the id_mapping parameter.
rst_action int 0x0-0xFFFFFFFF 0x0 Reset value of ACTION register.
rst_build_configa int 0x0-0xFFFFFFFF -d Reset value of BUILD_CONFIG register.
rst_gate_keeper int 0x0-0xFFFFFFFF 0x0 Reset value of GATE_KEEPER register.
rst_region_attributes_<x>a int 0x0-0xFFFFFFFF - Reset value of the REGION_<x>_ATTRIBUTES register, region <x> Secure state attributes.
rst_region_base_low_<x> int 0x0-0xFFFFFFFF - Reset value of the REGION_<x>_BASE_ADDRESS_LOW register, region <x> base memory address, low 32 bits. <x> is the filter unit number. There is no register for region 0 because the value is fixed.
rst_region_base_high_<x> int 0x0-0xFFFFFFFF - Reset value of the REGION_<x>_BASE_ADDRESS_HIGH register, region <x> base memory address, high 32 bits. There is no register for region 0 because the value is fixed.
rst_region_id_access_<x> int 0x0-0xFFFFFFFF - Reset value of the REGION_<x>_ID_ACCESS register, region <x> NSAID permissions.
rst_region_top_low_<x> int 0x0-0xFFFFFFFF - Reset value of the REGION_<x>_TOP_ADDRESS_LOW register, region <x> top memory address, low 32 bits. There is no register for region 0 because the value is fixed.
rst_region_top_high_<x> int 0x0-0xFFFFFFFF - Reset value of the REGION_<x>_TOP_ADDRESS_HIGH register, region <x> top memory address, high 32 bits.

TZC_400 - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies.

However, it does not implement:

  • The vnet bits[27:24] in FAIL_ID_<x> registers.
  • Any background logic for the speculation control register. This does not affect model behavior.

TZC_400 - subcomponents

This component contains TZFilterUnits and a TZDummyDevice.

TZFilterUnits
The TZC-400 has four TZFilterUnits. The BUILD_CONFIG register sets the configuration. The rst_build_config parameter controls the register.
TZDummyDevice
An internal dummy device that mimics RAZ/WI for TZFilterUnits. The system uses it when there is a permission violation and a bus returns Transaction OK.

TZC_400 - verification and testing

This component passes use tests with Linux operating systems.

a Configure master_id_from_label or id_mapping, rst_build_config, and rst_region_attributes_0 before running the model to set the desired behaviors. Otherwise, the system resets all region configuration registers, rst_action, and rst_gate_keeper to 0, and resets rst_build_config and rst_region_attributes_0 to sensible default values. Configure either id_mapping or master_id_from_label at model init, or a warning message appears.
b No default.
c The syntax of id_mapping is:

<masterid_0>:<nsaid_0>,<masterid_1>:<nsaid_1>,<masterid_n>:<nsaid_n>.

Separate the mapping pairs by ,. The masterid is the ID of the bus master, such as the parameter CLUSTER_ID on Cortex-A15/7, cluster_id port of Cortex-A15/7, or master_id parameter for Cortex-M3.

d The reset values vary with the system. See the system design documentation or system integration documentation. (0x3003F08 for AEMv8-A.)
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