ARM® CoreLink™ DMC-620 Dynamic Memory Controller. This model is written in C++.
DMC620 contains the following CADI targets:
DMC620 contains the following MTI components:
Limitations of the model:
- It does not support address striping.
- It works with linear addresses and not in rank,bank,row,column form.
- It includes error injection and detection mechanisms and syndrome registers support only for RAS error types 4 (ECC single-bit SRAM error) and 5 (ECC double-bit SRAM error).
- Scrubbing functionality is not provided.
- It does not implement direct read or write commands.
- It does not implement any performance counters.
The DMC-620 model has different interfaces to those in the hardware due to the level of abstraction of memory in Fast Models:
Like the hardware, the model has a slave port for configuring register accesses,
apb_pvbus_s, and an AXI interface for incoming memory transactions that are attempting to access memory that is managed by the DMC.
The hardware component translates incoming transactions on the AXI interface to a format that is conducive to accessing DRAM chips. The model performs TrustZone™ access control and models the DMC readiness state, but does not translate the transactions. If allowed, the model forwards incoming transactions to be handled by a memory storage handling component that works at the transaction level.
Table 4-60 Ports
||Signal||Master||A combined interrupt that is the logical OR of the other interrupts.|
||PVBus||Slave||Programmers interface to program and control the DMC-620.|
||Signal||Master||The DMC has detected a change in the architectural state.|
||Signal||Master||The DMC has detected a system request that has failed a permissions check and a previously detected assertion was not cleared.|
||PVBus||Master||DMC master port to memory.|
||Signal||Master||The DMC has detected and corrected a single bit error on the RAM access.|
||Signal||Master||The DMC has detected a double bit error on the RAM access.|
Table 4-61 Parameters
||false||Override default block-all behavior of DMC. Allow access to memory.|
||false||Always allow debug access to memory.|