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GIC600 component

GIC-600 IRI implementation. Single chip validation component variant that is limited to 265 PEs. This model is written in C++.

About

GIC600 and GIC600_Filter are minimal models of an ARM GIC-600 Generic Interrupt Controller, suitable for single-chip systems. They provide a simple configuration interface that allows designers to introduce GIC600-like functionality to their systems, while only implementing the architectural behavior, as defined by the GICv3 architecture.

All implementation-specific registers and functionality are unimplemented except for GICR_PWRR, for which an effectless but stateful implementation is present. This allows a power-aware software implementation to observe the correct value.

As with the other GIC components, there are two variants of the model with slightly different memory interfaces. Both GIC600 and GIC600_Filter have a pvbus_s port for register accesses and a pvbus_m port for the LPI-related traffic from redistributors and the ITS.

In addition, the GIC600_Filter variant has a pvbus_filtermiss_m port, to which any transaction coming on the pvbus_s port and not directed to a 4K page used by the GIC is forwarded unmodified. Such transactions are terminated in the component when using the GIC600 variant.

It is recommended to use the GIC600 variant in most cases.

GIC600 and GIC600_Filter contain the following CADI targets:

  • GIC600

GIC600 and GIC600_Filter contain the following MTI components:

Table 4-88 Ports

Name Protocol Type Description
cpu_active_s Signal Slave CPUActive pins.
po_reset Signal Slave Resets.
ppi_in_n Signal Slave Private peripheral interrupts (ID16-ID31) for cpu n, where 0 ≤ n ≤ 255.
pvbus_m PVBus Master Memory bus out: transactions generated by the IRI.
pvbus_s PVBus Slave Memory bus in: memory-mapped register accesses are accepted on this interface.
redistributor_m GICv3Comms Master Input from and output to CPU interface.
reset Signal Slave Resets.
spi_in Signal Slave Shared peripheral interrupts.
wake_request Signal Master Power management outputs.

Table 4-89 Parameters

Name Type Allowed values Default value Description
enabled bool true, false true Enable GICv3 functionality; when false the component is inactive.
print-memory-map bool true, false false Print memory map to stdout.
reg-base uint64_t 0-0xffffffffffffffff 0x2c010000 GIC-600 base address.
CPU-affinities string - - A comma separated list of dotted quads containing the affinities of all PEs connected to this IRI.
ARE-fixed-to-one bool true, false false GICv2 compatibility is not supported and GICD_CTLR.ARE_* is always one.
affinity-width string - 8.8.8.8 A dotted quad indicating the bitwidth of fields at each affinity level.
DS-behaviour int 0-2 2 GICD_CTLR.DS field behaviour: 0: RAZ/WI, 1: RAO/WI, 2: RW
SPI-blocks int 0-30 30 Number of SPI blocks supported by the IRI, each block contains 32 SPIs.
PPI-count int 8-16 16 Selects the number of PPIs available for each PE as 8 (id 22-27, 29,30), 12 (id 20-31) or 16 (id 16-31).
ITS-count uint8_t 0-16 1 Number of Interrupt Translation Services to be instantiated (0=none).
direct-lpi-support bool true, false false Enable support for LPI operations through GICR registers.
ITS-device-bits uint8_t 3-20 16 Number of bits supported for ITS device IDs.
ITS-ID-bits uint8_t 1-16 16 Number of interrupt bits supported by ITS.
ITS-collection-ID-bits uint8_t 1-14 8 Number of collection bits supported by ITS (optional parameter, 0 => 16bits support and GITS_TYPER.CIL=0).
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