You copied the Doc URL to your clipboard.

PL022_SSP component

This section describes the PL022_SSP component.

PL022_SSP - about

This LISA+ component is a model of an ARM PL022 Synchronous Serial Port (SSP) PrimeCell.

PL022_SSP contains the following CADI targets:

  • PL022_SSP

PL022_SSP contains the following MTI components:

Although the PL022_SSP component has clock input, it is not internally clock-driven. This is different to the equivalent hardware.

Note

This component is a preliminary release. It is provided as-is with the VE reference platform model, and is not a fully supported peripheral.

PL022_SSP - ports

This section describes the ports.

Table 4-128 PL022_SSP ports

Name Protocol Type Description
clk ClockSignal Slave Main PrimeCell SSP clock input
clkin ClockSignal Slave PrimeCell SSP clock input
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
rxd ValueState Slave PrimeCell SSP receive data
clkout ClockSignal Master Clock output
intr Signal Master Interrupt signaling
rorintr Signal Master Receive overrun interrupt
rtintr Signal Master Receive timeout interrupta
rx_dma_port PL080_DMAC_DmaPortProtocol Master PrimeCell SSP receive DMA port
rxintr Signal Master Receive FIFO service request port
tx_dma_port PL080_DMAC_DmaPortProtocol Master PrimeCell SSP transmit DMA port
txd ValueState Master PrimeCell SSP transmit data
txintr Signal Master Transmit FIFO service request

PL022_SSP - registers

This section describes the registers.

Table 4-129 PL022_SSP registers

Name Offset Access Description
SSPCR0 0x000 Read/write Control register 0
SSPCR1 0x004 Read/write Control register 1
SSPDR 0x008 Read/write FIFO data
SSPSR 0x00C Read only Status
SSPCPSR 0x010 Read/write Clock prescale
SSPIMSC 0x014 Read/write Interrupt mask set/clear
SSPRIS 0x018 Read only Raw interrupt status
SSPMIS 0x01C Read only Masked interrupt status
SSPICR 0x020 Write only Interrupt clear
SSPDMACR 0x024 Read/write DMA control
SSPeriphID0 0xFE0 Read only Peripheral ID bits[7:0]
SSPeriphID1 0xFE4 Read only Peripheral ID bits[15:8]
SSPeriphID2 0xFE8 Read only Peripheral ID bits[23:16]
SSPeriphID3 0xFEC Read only Peripheral ID bits[31:24]
SSPPCellID0 0xFF0 Read only PrimeCell ID bits[7:0]
SSPPCellID01 0xFF4 Read only PrimeCell ID bits[15:8]
SSPPCellID 0xFF8 Read only PrimeCell ID bits[23:16]
SSPPCellID3 0xFFC Read only PrimeCell ID bits[31:24]

PL022_SSP - verification and testing

The functions of this component have been tested individually by using a tailored test suite. The component has not been validated against a target operating system, but improved support is expected in the next release.

a

Not supported.

Was this page helpful? Yes No