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PL061_GPIO component

This section describes the General Purpose Input/Output (GPIO) component.

PL061_GPIO - about

ARM PrimeCell General Purpose Input/Output (PL061). This model is written in LISA+.

PL061_GPIO contains the following CADI targets:

  • PL061_GPIO

PL061_GPIO contains the following MTI components:

It provides eight programmable inputs or outputs. Ports of different widths can be created by multiple instantiation. In addition, an interrupt interface is provided to configure any number of pins as interrupt sources.

PL061_GPIO - ports

This section describes the ports.

Table 4-138 PL061_GPIO ports

Name Protocol Type Description
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
GPIO_In Value Slave Input linesa
GPIO_Intr Signal Master Interrupt signal indicating to an interrupt controller that an interrupt occurred in one or more of the GPIO_In lines.
GPIO_MIS Value Master Indicates the masked interrupt statusa
GPIO_Out Value Master Output linesa

PL061_GPIO - registers

This section describes the registers.

Table 4-139 PL061_GPIO registers

Name Offset Access Description
GPIODATA 0x000 - 0x3FC Read/write GPIO prime data register. The address offsets serve as a mask. Only bits[11:2] are valid as the mask.b
GPIODIR 0x400 Read/write Data direction register. Set for output, clear for input.
GPIOIS 0x404 Read/write Interrupt sense register. Set for level trigger, clear for edge trigger.
GPIOIBE 0x408 Read/write Bits set, both edges on corresponding pin trigger and interrupt.
GPIOIEV 0x40C Read/write Interrupt event register. Bit set for rising edge or high level trigger.
GPIOIE 0x410 Read/write Interrupt mask register.
GPIORIS 0x414 Read Raw interrupt status register.
GPIOMIS 0x418 Read Masked interrupt status register.
GPIOIC 0x41C Write Interrupt clear register.
GPIOAFSEL 0x420 Read/write Mode control select.
GPIOPeriphID0 0xfe0 Read Peripheral ID register.
GPIOPeriphID1 0xfe4 Read Peripheral ID register.
GPIOPeriphID2 0xfe8 Read Peripheral ID register.
GPIOPeriphID3 0xfec Read Peripheral ID register.
GPIOPCellID0 0xff0 Read PrimeCell ID register.
GPIOPCellID1 0xff4 Read PrimeCell ID register.
GPIOPCellID2 0xff8 Read PrimeCell ID register.
GPIOPCellID3 0xffc Read PrimeCell ID register.

PL061_GPIO - verification and testing

The functions of this component have been tested individually using a tailored test suite.

a Only the lower end eight bits[7:0] are used.

For writes, values written to the registers are transferred onto the GPOIT pins if the respective pins have been configured as output ports. Set certain pins in GPIO_Mask to high to enable writing. A similar process applies to reads.

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