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SMSC_91C111 component

This section describes the SMSC_91C111 component.

SMSC_91C111 - about

10/100 non-PCI Ethernet controller (SMSC 91C111). This model is written in C++.

SMSC_91C111 contains the following CADI targets:

  • SMSC_91C111

SMSC_91C111 contains the following MTI components:

It provides the register interface of the SMSC part and can be configured to act as an unconnected Ethernet port, or an Ethernet port connected to the host by an Ethernet bridge.

SMSC_91C111 - ports

This section describes the ports.

Table 4-181 SMSC_91C111 ports

Name Protocol Type Description
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
intr Signal Master Interrupt signaling
clock ClockSignal Slave Clock input, typically 25MHz, which sets the master transmit/receive rate
eth VirtualEthernet Master Ethernet port

SMSC_91C111 - parameters

This section describes the parameters.

Table 4-182 SMSC_91C111 parameters

Name Type Allowed values Default value Description
enabled bool true, false false Enables user-mode networking, for sending Ethernet frames between components.
mac_address string - '00:02:f7:ef:00:02' MAC address to use on host.
promiscuous bool true, false true Puts host Ethernet controller into promiscuous mode, for instance when sharing the Ethernet controller with the host OS.

SMSC_91C111 - mac_address parameter

This parameter has two options.

If a MAC address is not specified, when the simulator is run it takes the default MAC address, which is randomly-generated. This provides some degree of MAC address uniqueness when running models on multiple hosts on a local network.


DHCP servers allocate the IP addresses, but because they sometimes do this based on the MAC address provided to them, then using random MAC addresses might interact unfortunately with some DHCP servers.

SMSC_91C111 - registers

This component uses a banked register model of primarily 16-bit registers. There are also indirectly accessible registers for the PHY unit.

SMSC_91C111 - bank 0 registers

This section describes the bank 0 registers.

Table 4-183 SMSC_91C111 bank 0 registers

Name Offset Access Description
TCR 0x0 Read/write Transmit control
EPH 0x2 Read only Status of last transmitted frame
RCR 0x4 Read/write Receive control
COUNTER 0x6 Read/write MAC statistics
MIR 0x8 Read/write Memory information
RPCR 0xA Read/write Receive/PHY control
BANK 0xE Read/write Bank select

SMSC_91C111 - bank 1 registers

This section describes the bank 1 registers.

Table 4-184 SMSC_91C111 bank 1 registers

Name Offset Access Description
CONFIG 0x0 Read/write Configuration
BASE 0x2 Read/write Base address
IA0_1 0x4 Read/write MAC address 0, 1
IA2_3 0x6 Read/write MAC address 2, 3
IA4_5 0x8 Read/write MAC address 4, 5
GP 0xA Read/write General purpose
CONTROL 0xC Read/write Control
BANK 0xE Read/write Bank select

SMSC_91C111 - bank 2 registers

This section describes the bank 2 registers.

Table 4-185 SMSC_91C111 bank 2 registers

Name Offset Access Description
MMU_COMMAND 0x0 Read/write MMU commands
PNR 0x2 Read/write Packet number
ALLOCATED 0x3 Read/write Allocated packet number
FIFO_PORTS 0x4 Read/write Tx/Rx FIFO packet number
POINTER 0x6 Read/write Address to access in Tx/Rx packet
DATA 0x8 Read/write Data registera
INTERRUPT 0xC Read/write Interrupt status
INTERRUPT_MASK 0xD Read/write Interrupt mask
BANK 0xE Read/write Bank select

SMSC_91C111 - bank 3 registers

This section describes the bank 3 registers.

Table 4-186 SMSC_91C111 bank 3 registers

Name Offset Access Description
MT0_1 0x0 Read/write Multicast table 0, 1
MT2_3 0x2 Read/write Multicast table 2, 3
MT4_5 0x4 Read/write Multicast table 4, 5
MT6_7 0x6 Read/write Multicast table 6, 7
MGMT 0x8 Read/write Management interface
REVISION 0xA Read only Chip revision ID
ERCV 0xC Read/write Early receive
BANK 0xE Read/write Bank select

SMSC_91C111 - verification and testing

This component passes tests as part of the VE example system by using VE test suites and by booting operating systems.


The data register can be accessed as 8, 16 or 32 bits and adjusts the pointer accordingly.

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