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PL180_MCI component

This section describes the PL180_MCI component.

PL180_MCI - about

ARM PrimeCell Multimedia Card Interface (PL180). This model is written in LISA+.

PL180_MCI contains the following CADI targets:

  • PL180_MCI

PL180_MCI contains the following MTI components:

When paired with an MMC card model, the PL180_MCI component provides emulation of a flexible, persistent storage mechanism. The PL180_MMC component fully models the registers of the corresponding PrimeCell, but supports a subset of the functionality of the PL180:

  • The controller supports block mode transfers, but does not currently support streaming data transfer.
  • The controller can be attached to a single MMC device. The MMC bus mode and SDIO modes of the PL180 PrimeCell are not supported.
  • Command and Data timeouts are not simulated.
  • Payload CRC errors are not simulated.
  • The DMA interface present in the PL180 PrimeCell is not modeled.
  • Minimal timing is implemented within the model.

PL180_MCI - ports

This section describes the ports.

Table 4-151 PL180_MCI ports

Name Protocol Type Description
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
MCIINTR[0-1] Signal Master Interrupt request ports
mmc_m MMC_Protocol Master The MultiMediaCard (MMC) master port

PL180_MCI - registers

This section describes the registers.

Table 4-152 PL180_MCI registers

Name Offset Access Description
MCIPower 0x000 Read/write Power control register
MCIClock 0x004 Read/write Clock control register
MCIArgument 0x008 Read/write Argument register
MCICommand 0x00C Read/write Command register
MCIRespCmd 0x010 Read only Response command register
MCIResponse0 0x014 Read only Response register
MCIResponse1 0x018 Read only Response register
MCIResponse2 0x01C Read only Response register
MCIResponse3 0x020 Read only Response register
MCIDataTimer 0x024 Read/write Data timer
MCIDataLength 0x028 Read/write Data length register
MCIDataCtrl 0x02C Read/write Data control register
MCIDataCnt 0x030 Read only Data counter
MCIStatus 0x034 Read only Status register
MCIClear 0x038 write only Clear register
MCIMask0 0x03C Read/write Interrupt 0 mask register
MCIMask1 0x040 Read/write Interrupt 1 mask register
MCISelect 0x044 Read/write Secure Digital card select register
MCIFifoCnt 0x048 Read only FIFO counter
MCIFIFO 0x080 Read/write Data FIFO register
MCIPeriphID0 0xFE0 Read only Peripheral ID bits[7:0]
MCIPeriphID1 0xFE4 Read only Peripheral ID bits[15:8]
MCIPeriphID2 0xFE8 Read only Peripheral ID bits[23:16]
MCIPeriphID3 0xFEC Read only Peripheral ID bits[31:24]
MCIPCellID0 0xFF0 Read only PrimeCell ID bits[7:0]
MCIPCellID1 0xFF4 Read only PrimeCell ID bits[15:8]
MCIPCellID2 0xFF8 Read only PrimeCell ID bits[23:16]
MCIPCellID3 0xFFC Read only PrimeCell ID bits[31:24]

PL180_MCI - debug features

At compile time, you can enable command tracing within the PL180_MCI component by modifying the PL180_TRACE macro in the MMC.lisa file. This sends command and event trace to standard output. You can use this output to help diagnose device driver and controller-to-card protocol issues.

PL180_MCI - verification and testing

This component passes tests in conjunction with the ARM MMC reference model, and in the VE example with Boot Monitor and Linux drivers.

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