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PL370_HDLCD component
This section describes the PL370_HDLCD component.
PL370_HDLCD - about
ARM PrimeCell HD Color LCD Controller (Nominal Designation PL370). This model is written in LISA+.
PL370_HDLCD contains the following CADI targets:
- ClockTimerThread
- ClockTimerThread64
- PL370_HDLCD
- SchedulerThread
- SchedulerThreadEvent
PL370_HDLCD contains the following MTI components:
PL370_HDLCD - ports
This section describes the ports.
Table 4-169 PL370_HDLCD ports
Name | Protocol | Type | Description |
---|---|---|---|
clk_in |
ClockSignal | Slave | Master clock input, typically 24MHz, to drive pixel clock timing. |
display |
LCD | Master | Connection to visualization component. |
intr |
Signal | Master | Interrupt signaling line for flyback events. |
pvbus |
PVBus | Slave | Slave port for connection to PV bus master/decoder. |
pvbus_m |
PVBus | Master | DMA port for collecting video data from memory/framebuffer. |
PL370_HDLCD - parameters
This section describes the parameters.
Table 4-170 PL370_HDLCD parameters
Name | Type | Allowed values | Default value | Description |
---|---|---|---|---|
diagnostics |
int |
-
|
|
Diagnostics level. |
disable_snooping_dma |
bool |
true , false |
false |
Disable DMA snooping. |
force_frame_rate |
int |
-
|
|
Force frame rate to the value of the parameter in frames per simulated second, regardless of the input clock. When 0, use the input clock as a pixel clock. |
PL370_HDLCD - registers
This section describes the registers.
Table 4-171 PL370_HDLCD registers
Name | Offset | Access | Description |
---|---|---|---|
VERSION |
|
Read only | Version Register |
INT_RAWSTAT |
|
Read/write | Interrupt Raw Status Register |
INT_CLEAR |
|
Write only | Interrupt Clear Register |
INT_MASK |
|
Read/write | Interrupt Mask Register |
INT_STATUS |
|
Read only | Interrupt Status Register |
FB_BASE |
|
Read/write | Frame Buffer Base Address Register |
FB_LINE_LENGTH |
|
Read/write | Frame Buffer Line Length Register |
FB_LINE_COUNT |
|
Read/write | Frame Buffer Line Count Register |
FB_LINE_PITCH |
|
Read/write | Frame Buffer Line Pitch Register |
BUS_OPTIONS |
|
Read/write | Bus Options Register |
V_SYNC |
|
Read/write | Vertical Synch Width Register |
V_BACK_PORCH |
|
Read/write | Vertical Back Porch Width Register |
V_DATA |
|
Read/write | Vertical Data Width Register |
V_FRONT_PORCH |
|
Read/write | Vertical Front Porch Width Register |
H_SYNC |
|
Read/write | Horizontal Synch Width Register |
H_BACK_PORCH |
|
Read/write | Horizontal Back Porch Width Register |
H_DATA |
|
Read/write | Horizontal Data Width Register |
H_FRONT_PORCH |
|
Read/write | Horizontal Front Porch Width Register |
POLARITIES |
|
Read/write | Polarities Register |
COMMAND |
|
Read/write | Command Register |
PIXEL_FORMAT |
|
Read/write | Pixel Format Register |
RED_SELECT |
|
Read/write | Color Select Registers |
GREEN_SELECT |
|
Read/write | Color Select Registers |
BLUE_SELECT |
|
Read/write | Color Select Registers |
PL370_HDLCD - verification and testing
This component passes tests using Linux and bare metal code on a development model.
PL370_HDLCD - performance
Too fast a pixel clock can slow the rest of the simulation.