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PL370_HDLCD component

This section describes the PL370_HDLCD component.

PL370_HDLCD - about

ARM PrimeCell HD Color LCD Controller (Nominal Designation PL370). This model is written in LISA+.

PL370_HDLCD contains the following CADI targets:

PL370_HDLCD contains the following MTI components:

This section describes the ports.

Table 4-169 PL370_HDLCD ports

Name	Protocol	Type	Description
`clk_in`	ClockSignal	Slave	Master clock input, typically 24MHz, to drive pixel clock timing.
`display`	LCD	Master	Connection to visualization component.
`intr`	Signal	Master	Interrupt signaling line for flyback events.
`pvbus`	PVBus	Slave	Slave port for connection to PV bus master/decoder.
`pvbus_m`	PVBus	Master	DMA port for collecting video data from memory/framebuffer.

This section describes the parameters.

Table 4-170 PL370_HDLCD parameters

Name	Type	Allowed values	Default value	Description
`diagnostics`	`int`	`0x0`-`0x4`	`0x0`	Diagnostics level.
`disable_snooping_dma`	`bool`	`true`, `false`	`false`	Disable DMA snooping.
`force_frame_rate`	`int`	`0x0`-`0x78`	`0x32`	Force frame rate to the value of the parameter in frames per simulated second, regardless of the input clock. When 0, use the input clock as a pixel clock.

This section describes the registers.

Table 4-171 PL370_HDLCD registers

Name	Offset	Access	Description
VERSION	`0x0000`	Read only	Version Register
INT_RAWSTAT	`0x0010`	Read/write	Interrupt Raw Status Register
INT_CLEAR	`0x0014`	Write only	Interrupt Clear Register
INT_MASK	`0x0018`	Read/write	Interrupt Mask Register
INT_STATUS	`0x001C`	Read only	Interrupt Status Register
FB_BASE	`0x0100`	Read/write	Frame Buffer Base Address Register
FB_LINE_LENGTH	`0x0104`	Read/write	Frame Buffer Line Length Register
FB_LINE_COUNT	`0x0108`	Read/write	Frame Buffer Line Count Register
FB_LINE_PITCH	`0x010C`	Read/write	Frame Buffer Line Pitch Register
BUS_OPTIONS	`0x0110`	Read/write	Bus Options Register
V_SYNC	`0x0200`	Read/write	Vertical Synch Width Register
V_BACK_PORCH	`0x0204`	Read/write	Vertical Back Porch Width Register
V_DATA	`0x0208`	Read/write	Vertical Data Width Register
V_FRONT_PORCH	`0x020C`	Read/write	Vertical Front Porch Width Register
H_SYNC	`0x0210`	Read/write	Horizontal Synch Width Register
H_BACK_PORCH	`0x0214`	Read/write	Horizontal Back Porch Width Register
H_DATA	`0x0218`	Read/write	Horizontal Data Width Register
H_FRONT_PORCH	`0x021C`	Read/write	Horizontal Front Porch Width Register
POLARITIES	`0x0220`	Read/write	Polarities Register
COMMAND	`0x0230`	Read/write	Command Register
PIXEL_FORMAT	`0x0240`	Read/write	Pixel Format Register
RED_SELECT	`0x0244`	Read/write	Color Select Registers
GREEN_SELECT	`0x0248`	Read/write	Color Select Registers
BLUE_SELECT	`0x024C`	Read/write	Color Select Registers

This component passes tests using Linux and bare metal code on a development model.

Too fast a pixel clock can slow the rest of the simulation.

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