This section describes the RemapDecoder component.
RemapDecoder - about
Provides support for dynamically remappable regions of memory. This model is written in LISA+.
RemapDecoder - ports
This section describes the ports.
Table 4-181 RemapDecoder ports
||PVBus||Slave||For connection to PV bus master/decoder.|
||PVBus||Master||For connection to a component addressable with remap set.|
||PVBus||Master||For connection to a component addressable with remap clear.|
||StateSignal||Slave||Input permitting control of remap state.|
||TZSwitchControl||Internal port. Not for use.|
RemapDecoder - verification and testing
This component passes tests as part of the VE example system by using VE test suites and by booting operating systems.