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GIC500 component

This section describes the GIC500 component.

GIC500 - about

This is a model of r0p0 of the GIC-500 Generic Interrupt Controller (GIC) for distribution of interrupts. This model is written in C++.

GIC500 contains the following CADI targets:

  • GIC500

GIC500 contains the following MTI components:

This is a single-component implementation of the GICv3 architecture with support for 256 cores. You can configure the model to support a maximum of 32 clusters with eight cores per cluster. Use it with an ARMv8-A core to deliver interrupts. It supports a single Interrupt Translation Service for message-based interrupts. It supports the architectural features, but does not support the implementation defined features.

You must configure some parameters in order to use the GIC500 component. For example:

    gic500: GIC500(
        "num_clusters" = 2, 
        "cpus_per_cluster_0" = 4, 
        "cpus_per_cluster_1" = 4, 
        "reg-base" = 0x2c200000, 
        "SPI-count" = 256 
    );

GIC500 - ports

This table describes the GIC500 ports.

Table 4-84 GIC500 ports

Name Protocol Type Description
cfgsdisable Signal Slave Disable some SPI signals.
cpu_active_n[8] Signal Slave cpu_active pins of cluster n. 0 <= n <= 31.
po_reset Signal Slave Power-on reset.
ppix_in_n[8] Signal Slave Private peripheral interrupts of cluster n. 0 <= n <= 31. 16 <= x <= 31.
pvbus_m PVBus Master Memory bus out: transactions generated by the IRI.
pvbus_s PVBus Slave Memory bus in: this interface accepts memory-mapped register accesses.
redistributor_n[8] GICv3Comms Master Input from and output to the CPU interface for cluster n. 0 <= n <= 31.
reset Signal Slave Reset.
spi_in[988] Signal Slave Shared peripheral interrupts.
wake_request_n[8] Signal Master Power management outputs of cluster n. 0 <= n <= 31.

GIC500 - parameters

This table describes the GIC500 parameters.

Table 4-85 GIC500 parameters

Name Type Default value Description
cpus_per_cluster_n int 1 Number of cores in cluster n. 0 <= n <=31.
GICD_ITARGETSR-RAZWI bool 0x0 If true, the GICD_ITARGETS registers are RAZ/WI
ITS-count int 0x1 Number of Interrupt Translation Services to be instantiated (0=none)
ITS-device-bits int 0x10 Number of bits supported for ITS device IDs.
ITS-threaded-command-queue bool 0x1 Enable execution of ITS commands in a separate thread which is sometimes required for cosimulation
SPI-count int 0xe0 Number of SPIs that are implemented.
delay-ITS-accesses bool 0x1 Delay accesses from the ITS until GICR_SYNCR is read.
delay-redistributor-accesses bool 0x1 Delay memory accesses from the redistributor until GICR_SYNCR is read.
enable_protocol_checking bool 0x0 Enable/disable protocol checking at cpu interface
enabled bool 0x1 Enable GICv3 functionality; when false the component is inactive.
has-two-security-states bool 0x1 If true, has two security states
num_clusters int 0x1 Number of implemented affinity level1 clusters
print-memory-map bool 0x0 Print memory map to stdout
redistributor-threaded-sync bool 0x1 Enable execution of redistributor delayed transactions in a separate thread which is sometimes required for cosimulation
reg-base int 0x2c010000 GIC500 base address
using-generated-memorymap bool 0x1 Use the generated memorymap for the GIC500 and warn if superfluous parameters are passed
wakeup-on-reset bool 0x0 Go against specification and start redistributors in woken-up state at reset. This allows software that was written for previous versions of the GICv3 specification to work correctly. This should not be used for production code or when the distributor is used separately from the core fast model.
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