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SMMUv3AEM component

This section describes the SMMUv3AEM component.

SMMUv3AEM - about

The SMMUv3 Architecture Envelope Model component is an architectural model that implements the SMMUv3.0, SMMUv3.1, and SMMUv3.2 architectures for I/O virtualization of devices, except for the list of limitations below.

SMMUv3AEM contains the following CADI targets:

  • SMMUv3AEM

SMMUv3AEM contains the following MTI components:

The SMMUv3 specifies that input addresses are conceptually 64 bits. The SMMUv3AEM model assumes that the input address is 64 bits. If the SoC has less than 64 bits as an input address bus then if the SoC wants to use the high address space (and use TT1) then it must sign extend the address from the upstream peripherals to get to 64 bits.

The SMMUv3AEM model deals with groups of transactions with the same attributes and a similar range of addresses. The mapping used is remembered by the bus infrastructure and is used for subsequent sufficiently similar transactions without requiring intervention from the SMMU model, and so will not be traced, for instance. The range of addresses that the mapping is valid for is determined by the SMMU model, depending on architectural and model-implementation details. However, as it is unaware of any sign-extension then the mapping that the SoC does, the SoC is responsible for subsequently narrowing the range of addresses for which this mapping is valid. Typically, this will be done automatically when using PVBusMapper.

The model has the following limitations:

  • It does not support:
    • RAS.
    • Power control.
    • AMBA® stash operations and destructive read operations are not supported on PVBus and also are not supported by the device.
    • PCIe-NoSnoop transactions.
  • The PMU has limited functionality. Only a subset of the architecturally mandatory events are supported, as indicated by the SMMU_PMCG_CEID0 fields. The PMU is intended for demonstration purposes only and for driver development.
  • Secure Virtualization is not implemented for SMMUv3.2.

Notes

  • A bad configuration renders the model inactive.
  • Some configurations can be adjusted by configuration pins. These are only sampled at the negative edge of the reset pin. If you want to use these pins then you must drive them before sending a negative edge on the reset pin. During simulation_reset the component driving them must also drive this transition again.
  • Debug reads to the registers do not disturb the state.
  • Writes to registers with Update flags, including debug writes, are ignored if the Update flag is already set to one.
  • Debug and real accesses to the registers must be 32 or 64 bits.
  • MSIs are issued using attributes determined by the parameter msi_attribute_transform, whilst Event queue writes will always be issued with ExtendedID=0, UserFlags=0, MasterID=0xFFFFffff. Thus, if your system needs to distinguish MSI writes from Event queue writes, it may do so using this mechanism.
  • If your system does table walks and queue accesses through TBU0 (separate_tw_msi_qs_port == false), then care must be taken to distinguish table walk and queue traffic (with MasterID=0xFFFFffff) from normal translated traffic.
  • If SMMU_IDR1.TABLES_PRESET or SMMU_IDR1.QUEUES_PRESET is set then see parameter PRESET_REL_base_address and the parameters it mentions. Embedded implementations of the SMMU are allowed to have the queues/stream table in a 'close' RAM, either on-chip or in the SMMU itself. For the model, it is up to the integrator to supply this memory and for the SMMU model to be able to access. Thus if the actual hardware has the memory built into the SMMU then it will be necessary for the integrator to wrap this model with a bus decoder and a memory model to more closely model the embedded implementation.

SMMUv3AEM - ports

This section describes the ports.

Table 4-186 SMMUv3AEM - ports

Name Protocol Type Description
clk_in ClockSignal Slave Clock signal
conf_reset_of_SMMU_GBPA_ABORT Signal Slave System reset value of SMMU_GBPA.ABORT.
conf_reset_of_SMMU_S_GBPA_ABORT Signal Slave System reset value of SMMU_S_GBPA.ABORT.
conf_system_supports_btm Signal Slave System supports BTM and will be reflected in the IDR registers. This signal can override the value set by the parameters configuring the IDR registers. If BTM (Broadcast Table Maintenance) is not supported then DVM messages will be ignored.
conf_system_supports_cohacc Signal Slave System supports COHACC and will be reflected in the IDR registers. This signal can override the value set by the parameters configuring the IDR registers. If COHACC is set then page walks and SMMU-generated accesses will have the required shareability set, otherwise they will be marked as non-shareable.
conf_system_supports_httu Signal Slave System supports HTTU and will be reflected in the IDR registers. See parameter support_for_httu_when_starts_disallowed for the use of this signal.
conf_system_supports_sev Signal Slave System supports SEV and will be reflected in the IDR registers. This signal can override the value set by the parameters configuring the IDR registers.
identify SMMUv3AEMIdentifyProtocol Master Map the transaction to the tuple (StreamID, SubstreamID, SubstreamIDValid, SSD). See also parameter howto_identify.
irq_out_command_queue_sync_ns Signal Master Pulsed interrupt output signal for non-secure CMD_SYNC having a completion signal of SIG_IRQ.
irq_out_command_queue_sync_s Signal Master Pulsed interrupt output signal for secure CMD_SYNC having a completion signal of SIG_IRQ.
irq_out_event_queue_ns Signal Master Pulsed interrupt output signal for the non-secure event queue becoming non-empty.
irq_out_event_queue_s Signal Master Pulsed interrupt output signal for the secure event queue becoming non-empty.
irq_out_gerror_ns Signal Master Pulsed interrupt output signal for non-secure SMMU_GERROR(N) signalling an error.
irq_out_gerror_s Signal Master Pulsed interrupt output signal for secure SMMU_GERROR(N) signalling an error.
irq_out_ns Signal Master Pulsed interrupt output signal combined from all non-secure interrupts. This delivers a pulse if any of the interrupt pins of the specified world also deliver a pulse. SW will have to poll all the different reasons to see why it was delivered.
irq_out_pmcg_ns_as_value Value Master Non-secure PMCG interrupt value port. Value port representing a set of Performance Monitor Counter Group interrupts. There is an unknown number of PMCGs and so an unknown number of PMCG interrupts. There may not necessarily even be an interrupt per group. We export the interrupt to be generated as unsigned. The pmcg_index is exported on the top 16 bits and the pmcg_counter (that overflowed) on the bottom 16 bits.
irq_out_pmcg_s_as_value Value Master Secure PMCG interrupt value port. Value port representing a set of Performance Monitor Counter Group interrupts. There is an unknown number of PMCGs and so an unknown number of PMCG interrupts. There may not necessarily even be an interrupt per group. We export the interrupt to be generated as unsigned. The pmcg_index is exported on the top 16 bits and the pmcg_counter (that overflowed) on the bottom 16 bits.
irq_out_pri_queue Signal Master Pulsed interrupt output signal for the PRI queue.
irq_out_s Signal Master Pulsed interrupt output signal combined from all secure interrupts. This delivers a pulse if any of the interrupt pins of the specified world also deliver a pulse. SW will have to poll all the different reasons to see why it was delivered.
pvbus_control_s PVBus Slave Register slave port.
pvbus_id_routed_m PVBus Master This is a special "id-routed" port for transmitting ATC invalidates and PRI Responses upstream into the PCIe EndPoints, it is not a normal bus. The Fast Models ATC invalidate protocol specifies how to route and deal with this port. It is assumed that the StreamID can uniquely route the transaction if there are multiple PCIe Root Complexes.
pvbus_m[64] PVBus Master The TBU master ports that carry transactions that have been translated from the correspondingly numbered pvbus_s[] port.
pvbus_m_tw_msi_qs PVBus Master Master port used for Table Walks, MSIs and Queue access when separate_tw_msi_qs_port==true.
pvbus_s[64] PVBus Slave The TBU slave ports that receive transactions to be translated. They will exit the SMMU through the same numbered pvbus_m[] port.
reset_in Signal Slave Reset signal
sev_out Signal Master Event signal

SMMUv3AEM - parameters

This section describes the parameters.

Table 4-187 SMMUv3AEM parameters

Name Type Allowed values Default value Description
PRESET_REL_base_address int 0x0-0xFFFFffffFFFFffff 0x0

If using preset addresses (SMMU_IDR1.QUEUES_PRESET or SMMU_IDR1.TABLES_PRESET) then the queue and table base registers become fixed.

If SMMU_IDR1.REL is true then the addresses are relative to the base of the register file and this parameter tells the model what address to add to the queue/table addresses to calculate the actual address.

This is intended for 'embedded implementations' where the memory for these structures are held either within the SMMU itself or in a 'close' RAM. The SMMUv3 model itself does not contain any memory model and it is up to the integrator to supply a memory at the appropriate address.

See also:

  • TABLES_PRESET_smmu_strtab_base
  • TABLES_PRESET_smmu_strtab_base_cfg
  • TABLES_PRESET_smmu_s_strtab_base
  • TABLES_PRESET_smmu_s_strtab_base_cfg
  • QUEUES_PRESET_smmu_cmdq_base
  • QUEUES_PRESET_smmu_s_cmdq_base
  • QUEUES_PRESET_smmu_eventq_base
  • QUEUES_PRESET_smmu_s_eventq_base
  • QUEUES_PRESET_smmu_priq_base
QUEUES_PRESET_smmu_cmdq_base int 0x0-0xFFFFffffFFFFffff 0x0

If SMMU_IDR1.QUEUES_PRESET == 1 then this is the value that appears in SMMU_CMDQ_BASE and SMMU_CMDQ_BASE becomes read-only.

See also parameter PRESET_REL_base_address.

QUEUES_PRESET_smmu_eventq_base int 0x0-0xFFFFffffFFFFffff 0x0

If SMMU_IDR1.QUEUES_PRESET == 1 then this is the value that appears in SMMU_EVENTQ_BASE and SMMU_EVENTQ_BASE becomes read-only.

See also parameter PRESET_REL_base_address.

QUEUES_PRESET_smmu_priq_base int 0x0-0xFFFFffffFFFFffff 0x0

If SMMU_IDR1.QUEUES_PRESET == 1 and SMMU_IDR0.PRI == 1 then this is the value that appears in SMMU_PRIQ_BASE and SMMU_PRIQ_BASE becomes read-only.

See also parameter PRESET_REL_base_address.

QUEUES_PRESET_smmu_s_cmdq_base int 0x0-0xFFFFffffFFFFffff 0x0

If SMMU_IDR1.QUEUES_PRESET == 1 and SMMU_S_IDR1.SECURE_IMPL == 1 then this is the value that appears in SMMU_S_CMDQ_BASE and SMMU_S_CMDQ_BASE becomes read-only.

See also parameter PRESET_REL_base_address.

QUEUES_PRESET_smmu_s_eventq_base int 0x0-0xFFFFffffFFFFffff 0x0

If SMMU_IDR1.QUEUES_PRESET == 1 and SMMU_S_IDR1.SECURE_IMPL == 1 then this is the value that appears in SMMU_S_EVENTQ_BASE and SMMU_S_EVENTQ_BASE becomes read-only.

See also parameter PRESET_REL_base_address.

SMMU_AIDR uint32_t 0x0-0xFFFFffff 0 Contains the Major and Minor architectural revisions numbers.
SMMU_IDR0 uint32_t 0x0-0xFFFFffff - The following fields are further combined with the port conf_system_supports_{sev,httu,btm,cohacc}:
  • sev
  • httu
  • btm
  • cohacc
SMMU_IDR1 uint32_t 0x0-0xFFFFffff - SMMU_IDR1.
SMMU_IDR2 uint32_t 0x0-0xFFFFffff 0 Holds the BA_VATOS field.
SMMU_IDR3 uint32_t 0x0-0xFFFFffff 0 Reserved.
SMMU_IDR4 uint32_t 0x0-0xFFFFffff 0 implementation defined.
SMMU_IDR5 uint32_t 0x0-0xFFFFffff 0 Contains, amongst others the output address encoded size (OAS).
SMMU_IIDR uint32_t 0x0-0xFFFFffff 0 Contains fields for the implementer, product revision, etc.
SMMU_MPAMIDR int 0x0-0xFFFFffff 0x0

SMMUv3.2. If SMMU_IDR3.MPAM == 1 then SMMU_MPAMIDR holds further ID information for Memory Partitioning And Monitoring (MPAM) extension.

This is optional in SMMUv3.2 and is backported to SMMUv3.1.

SMMU_S_IDR0 uint32_t 0x0-0xFFFFffff 0 Secure IDR0 register.
SMMU_S_IDR1 uint32_t 0x0-0xFFFFffff - Indicates if there is a secure side by bit 31.
SMMU_S_IDR2 uint32_t 0x0-0xFFFFffff 0 Reserved.
SMMU_S_IDR3 uint32_t 0x0-0xFFFFffff 0 Reserved.
SMMU_S_IDR4 uint32_t 0x0-0xFFFFffff 0 implementation defined.
SMMU_S_MPAMIDR int 0x0-0xFFFFffff 0x0

SMMUv3.2: If SMMU_IDR3.MPAM == 1 then SMMU_S_MPAMIDR holds further ID information for Memory Partitioning And Monitoring (MPAM) extension.

This is optional in SMMUv3.2 and is backported to SMMUv3.1.

TABLES_PRESET_smmu_s_strtab_base int 0x0-0xFFFFffffFFFFffff 0x0

If SMMU_IDR1.TABLES_PRESET == 1 and SMMU_S_IDR1.SECURE_IMPL == 1 then this is the value that appears in SMMU_S_STRTAB_BASE and SMMU_S_STRTAB_BASE becomes read-only.

See also parameter PRESET_REL_base_address.

TABLES_PRESET_smmu_s_strtab_base_cfg int 0x0-0xFFFFffff 0x0

If SMMU_IDR1.TABLES_PRESET == 1 and SMMU_S_IDR1.SECURE_IMPL == 1 then this is the value that appears in SMMU_S_STRTAB_BASE_CFG and SMMU_S_STRTAB_BASE_CFG becomes read-only.

See also parameter PRESET_REL_base_address.

TABLES_PRESET_smmu_strtab_base int 0x0-0xFFFFffffFFFFffff 0x0

If SMMU_IDR1.TABLES_PRESET == 1 then this is the value that appears in SMMU_STRTAB_BASE and SMMU_STRTAB_BASE becomes read-only.

See also parameter PRESET_REL_base_address.

TABLES_PRESET_smmu_strtab_base_cfg int 0x0-0xFFFFffff 0x0

If SMMU_IDR1.TABLES_PRESET == 1 then this is the value that appears in SMMU_STRTAB_BASE_CFG and SMMU_STRTAB_BASE_CFG becomes read-only.

See also parameter PRESET_REL_base_address.

all_error_messages_through_trace bool true, false false

Some conditions in the SMMU are so unusual that the software programming the SMMU has done something wrong. At this point messages are output to either ArchMsg.Error.* or ArchMsg.Warning.* or to the error stream of the simulator. Outputting to the error stream of the simulator may cause it to return with a non-zero exit status.

If you set this option to true then instead of using the error stream of the simulator it will always use a trace stream, allowing the simulation to exit with a zero exit status.

allow_non_secure_access_to_SMMU_S_INIT bool true, false false

If the system has no software operating as a secure agent then set this parameter. This allows non-secure accesses to the SMMU_S_INIT register and allows the non-secure software to reset the TLB, clearing out any 'secure' TLB entries.

If the SMMU does not implement the security extensions (SMMU_S_IDR1.SECURE_IMPL == 0) then this parameter is ignored.

cmdq_max_number_of_commands_to_buffer uint32_t 0x0-0xFFFFffff 10 The command queues can buffer fetched commands before issuing them. This parameter is roughly the maximum number of commands to do this for. The programmer visible effects are that just because the CONS pointer shows a command has been consumed does not necessarily mean that it has been issued (and completed). Higher values will accentuate this effect.
enable_device_id_checks bool true, false true If this parameter is true then the DeviceIDs seen by the GIC are:
  • for client devices: DeviceID = StreamID + translated_device_id_base
  • for SMMU-generated MSIs: smmu_msi_device_id
This parameter enables two checks:
  • If the DeviceID is used in output_attribute_transform then if it overflows 32 bits then the model will warn. If the DeviceID is not used then it is assumed that the external agent that forms the DeviceID will warn if it overflows.
  • If the SMMU supports MSIs, then the model will check that the GIC will be able to distinguish an MSI generated by the SMMU from one generated by a client device.
As the exact mechanism to determine the DeviceID is in the system and not necessarily under control of the SMMU then you can disable these warnings using this parameter. See also the parameters: output_attribute_transform and msi_attribute_transform.
howto_identify string - "use-identify"

If use-identify then will use the identify port to determine the SSD, StreamID, SubStreamID of a transaction. Otherwise, this string extracts them from the transaction's attributes.

Examples:

  • SEC_SID=ExtendedID[63], SSV=ExtendedID[62], SubstreamID=ExtendedID[51:32], StreamID=ExtendedID[31:0]

  • nSEC_SID=ExtendedID[63], StreamID=ExtendedID[55:24], nSSV=ExtendedID[20], SubstreamID=ExtendedID[19:0]

SEC_SID is one bit wide, true if StreamID is secure. SSV is one bit wide, true if SubstreamID is valid.

The alternative symbols nSEC_SID and nSSV have the negative logic to SEC_SID and SSV. You must not use the negative and positive logic for the same symbol at the same time. However, just because you use negative logic for one symbol does not force you to use negative logic for the other.

SubstreamID is 20 bits wide and StreamID is 32 bits.

More complex examples:

StreamID[31:24]=0, StreamID[23:0]=ExtendedID[23:0], SSV=1[0], ...

Available attributes: ExtendedID, MasterID, UserFlags.

httu_memory_types_supported string - "rawaWB, raWB, waWB, naWB"

This is a comma-separated list of memory types that are implementation defined as supporting HTTU. However, the system must have Far Atomic support for the specified memory address and memory type.

Device types: nGnRnE, nGnRE, nGRE, GRE.

Normal memory types are composed of an 'inner' and an 'outer' cacheability. The model only supports types where the inner and outer are identical.

Normal non-cacheable types: nc_nb, nc

Cacheable types are of the form (na?|(ra)?(wa)?)(WT|WB)(tr)?

  • na/ra/wa - no/read/write allocate
  • WT/WB - write through/write back
  • tr - transient

Exceptions:

  • na and tr are incompatible
  • without na then you must specify at least one of ra/wa.

Example: WT is illegal, raWT is legal.

rawaWB is always supported and it is optional.

Examples:

  • "rawaWB, raWB, waWB, naWB" - only the WB type is supported
  • "nc" - rawaWB and the normal non-cacheable type are supported.
imp_def_L1CD_L2Ptr_out_of_range unsigned 0x0-0x3 0

If an L1CD.L2Ptr is out of range of IAS/OAS as appropriate then what happens is controlled by this parameter:

  • 0 - if is an IPA, then Stage 2 Translation Fault, if is a PA then truncate to OAS

  • 1 - generate C_BAD_SUBSTREAMID if an IPA and > IAS, or if a PA and > OAS.

  • 2 - generate C_BAD_SUBSTREAMID if an IPA and > IAS, or F_CD_FETCH if a PA and > OAS.

  • 3 - truncate the IPA or PA to IAS/OAS as appropriate

NOTE that if the model is configured as SMMUv3.1 then this parameter is ignored, and behaves as though this parameter was set to 1. The SMMUv3.1 architecture actually allows more behaviors but the model will only implement this one.

NOTE that the SMMUv3.0 allows more behaviors than can be expressed by this parameter.

imp_def_PID0 unsigned 0x0-0xFF 0x83 If imp_def_has_PID_CID is true then this is the PID0 value.
imp_def_PID1 unsigned 0x0-0xFF 0xb4 If imp_def_has_PID_CID is true then this is the PID1 value.
imp_def_PID2 unsigned 0x0-0xFF 0xb If imp_def_has_PID_CID is true then this is the PID2 value.
imp_def_PID3 unsigned 0x0-0xFF 0x0 If imp_def_has_PID_CID is true then this is the PID3 value.
imp_def_PID4 unsigned 0x0-0xFF 0x4 If imp_def_has_PID_CID is true then this is the PID4 value.
imp_def_S1ContextPtr_out_of_range unsigned 0x0-0x5 0

If an STE is fetched that uses a stage 1 then if Stage 1 only and S1ContextPtr > OAS, or Stage 1+2 and S1ContextPtr > IAS then what happens is implementation defined and this parameter controls the behavior:

  • 0 - stage 1 only - C_BAD_STE, stage 1+2 - C_BAD_STE
  • 1 - stage 1 only - C_BAD_STE, stage 1+2 - truncate to IAS
  • 2 - stage 1 only - truncate to OAS, stage 1+2 - C_BAD_STE
  • 3 - stage 1 only - truncate to OAS, stage 1+2 - truncate to IAS
  • 4 - stage 1 only - truncate to OAS, stage 1+2 - Stage 2 translation fault
  • 5 - stage 1 only - C_BAD_STE, stage 1+2 - Stage 2 translation fault

The architecture also allows for F_CD_FETCH, but the model does not support this.

NOTE that in SMMUv3.1 then the only allowed values of this parameter are 0 or 5.

imp_def_alloccfg unsigned 0x0-0x0 0

ALLOCCFG overrides the read/write/transient hints on cacheable types. However these are hints and an implementation may choose to treat them differently.

  • 0 - apply the alloc hints as architecturally specified
  • 1 - ignore all ALLOCCFG fields (treated as zero).
imp_def_ats_attribute_stashing int 0-2 0x0

The SMMU architecture allows an ATS request to return the attributes with which to make the Translated Access. PCIe does not define any transaction attributes in the ARM sense and so the mechanism for doing this is IMP DEF. Usually this would be done by packing them into the high order address bits of the return response.

In the model, then the representation of the ATS reply returns the attributes directly and it is up to the ATC whether it wants to use them or not. The parameter configures what to place in those architectural attributes in the ATS Reply.

  • 0 -- the architectural attributes
  • 1 -- Inner Write Back, Outer Write Back, Inner Shared, read and write allocate, User-Data
  • 2 -- Inner Write Back, Outer Write Back, Outer Shared, read and write allocate, User-Data

The SMMU cannot force an ATC to use these attributes, it is simply the attributes that are returned in the non-PCIe part of the ATS reply.

imp_def_cohacc_effect unsigned 0x0-0x1 0

SMMU_IDR0.COHACC is a system property. However, the exact nature of the transactions that the SMMU emits is an implementation defined property when COHACC == 0:

  • 0 - COHACC == 0 forces the output attributes of SMMU-generated accesses to non-shared.
  • 1 - The only effect of COHACC is what is reported in SMMU_IDR0.COHACC and has no effect on the output attributes of SMMU-generated accesses.
imp_def_has_PID_CID bool true, false true If this is true then the SMMU model will have the standard PID/CID ID registers. Only the PID0…PID4 registers can be customized and the parameters imp_def_PID0imp_def_PID4 are used.
imp_def_reset_unknown_fields_to_zero bool true, false false Many fields and registers in the SMMUv3 architecture reset to an unknown value. However, many implementations will choose to reset to 0. By setting this parameter to true then those fields will be initialised to zero.
imp_def_split_ATS_attributes_is_stage1 bool true, false false If using split stage ATS, then it is implementation defined whether the stage 1 attributes are returned to the ATS request or stage 2. This only has a meaning if the SMMU can stash attributes in the ATS response.
imp_def_truncate_out_of_range_streamids_on_invalidate_commands bool true, false false

If this parameter is true then the StreamID fields of the following commands will be truncated to (S_)SIDSIZE:

  • CMD_ATC_INV
  • CMD_CFGI_STE
  • CMD_CFGI_STE_RANGE
  • CMD_CFGI_CD
  • CMD_CFGI_CD_ALL
Otherwise, these commands will NOP.
imp_def_v3_atos_fault unsigned 0-1 0

For an IPA to PA ATOS translation that encounters a Stage 1 Address Size Fault then the PAR.REASON field reports:

  • in SMMUv3.1, 'Stage 1' (0)
  • in SMMUv3.0, 'Stage 1' (0) or 'Input' (3) depending on the implementation.

This parameter is ignored for SMMUv3.1.

For SMMUv3.0, the values are:

  • 0 - report as 'Input' (3)
  • 1 - report as 'Stage 1' (0).
mpam_attribute_transform string - "ExtendedID[62:55]=MPAM_PMG, ExtendedID[54:39]=MPAM_PARTID, ExtendedID[38]=MPAM_NS"

If MPAM is supported, then this is the transform applied to _all_ downstream transactions to transport the MPAM information. If MPAM is not supported then the transform is not applied, however, it is still checked that it is syntactically checked. If MPAM is supported in one security state, it is considered to be supported in all security states, even if that state has PARTID_MAX == 0 or PMG_MAX == 0 and the transform will be applied.

NOTE that for translated transactions from client devices then: MPAM_NS = ! SEC_SID

msi_attribute_transform string - "ExtendedID[31:0]=smmu_msi_device_id, MasterID=0xFFFFffff"

The SMMU will use this parameter to determine the MSI output attributes of MSIs it generates itself:

  • MasterID
  • UserFlags
  • ExtendedID of the transaction to use.

This is a set of comma-separated transforms on the output attributes. The right hand side of the transform is:

  • a numeric literal (or a slice of a literal)
  • the parameter smmu_msi_device_id
  • the symbol 'interrupt_kind':
    • 0/1 - EVENTQ Secure/Non-secure
    • 2 - PRIQ
    • 3/4 - CMD_SYNC Secure/Non-secure
    • 5/6 - GERROR Secure/Non-secure

Example:

UserFlags[15:0]=smmu_msi_device_id[31:16], MasterID[15:0]=smmu_msi_device_id[15:0], ExtendedID=0

This transform might be used as part of a system-specific way of determining the DeviceID that is passed to the GIC to distinguish MSIs generated by the SMMU from those generated by client devices of the SMMU.

See also: output_attribute_transform and enable_device_id_checks.

msi_ra_wa_tr uint32_t 0-7 7

A bitmap of the Read Allocation, Write Allocate and Transient hints for MSIs to cacheable memory:

  • bit[0] Transient
  • bit[1] Write Allocate
  • bit[2] Read Allocate

If not Write Allocate then it will be forced to Read Allocate as a limitation of AMBA.

number_of_ports unsigned 1-64 1 The number of port pairs that the SMMU has.
out_of_range_CMD_ATC_INV_Size unsigned 0-1 0

If CMD_ATC_INV.Size > 52 then the model is allowed to:

  • 0 - raise CERROR_ILL
  • 1 - treat as NOP

The architecture also allows for an unknown invalidate size to be used as well but the model does not support this.

output_attribute_transform string - "ExtendedID[31:0]=DeviceID"

Transform the downstream attributes of a translated transaction:

  • "" or "none" - the input and output attributes are identical.
  • A specification of how to alter the output attributes. An example is: "ExtendedID[15:0]=DeviceID[15:0], UserFlags[31]=nSSV, UserFlags[19:0]=SubstreamID"

The attributes that can appear on the left hand side of the transform are ExtendedID, MasterID and UserFlags.

The source attributes that can be used are:

  • ExtendedID/MasterID/UserFlags - the incoming attributes.
  • DeviceID - StreamID + translated_device_id_base
  • StreamID/SubstreamID/SSV/SEC_SID
  • nSEC_SID/nSSV - the negative logic versions.
  • St1PBHA/St2PBHA - the Page Based Hardware Attributes from any used leaf descriptors (or zero if not used).
  • STE_IMPDEF1 - STE[127:116]

The right hand side may also contain numeric literals. Any bits of the attributes that have no transform specified are retained from the input.

percent_commit uint32_t 0-100 20

Percentage of times that a read of a register with Update will commit the update. 0 means commit immediately.

percent_commit_Update_clear uint32_t 0-100 20 Percentage of times that a read of a register with a pending Update clear will lower the Update flag.
pmu string - ""

What to instantiate as a PMU.

Note that all events and counters are intended for demonstration purposes only and should not be treated as in any way reflecting accurate values for a real implementation. The model's internal representation of actions differ significantly from real hardware and the particular value obtained from the counters should not be used for benchmarking.

Values of this parameter are:

  • "" - no PMU
  • "distributed-0"

distributed-0:

  • a PMCG per TBU (number_of_ports, up to 63 ports)
  • a single PMCG for a TCU
  • Connect a debugger to see the configuration.
ports_that_ignore_PnU_InD_on_transactions_with_no_SubstreamID string - ""

Some bus systems (notably PCIe) do not support marking a transaction as Privileged/User or Instruction/Data unless the transaction has a SubstreamID.

This accepts a comma-separated list of numbers and ranges, for example:

0, 10-12, 15

If the number P is named in this list then the upstream pvbus_s[P] will have all transactions with no Substream considered to be User and Data.

prefetch_only_requests int 0-2 0x0

The simulator supports 'prefetch-only' DMI requests. These can occur for any reason at any time and are intended to be invisible to the end execution of the model and to the user. The SMMU can be configured how to respond:

  • 0 -- Deny all prefetch-only requests.
  • 1 -- Use debug requests for any page table walks, form and use debug TLB/cache entries, any faults will not record, but deny the prefetch request.
  • 2 -- Treat prefetch-only requests like normal transactions, use normal page table walk transactions, use and form normal TLB/cache entries, faults will alter the programmer visible state of the SMMU.

0 is the safest.

1 treats the access like a debug request and requires that debug page table walks are treated correctly downstream. Any descriptors that need HTTU to allow the transaction to proceed will fail the request.

2 is dangerous as it will make real transactions and report faults for prefetch-only transactions that may have no correspondence to the hardware.

reset_value_of_SMMU_GBPA uint32_t 0x0-0xFFFFffff 0 Reset value of SMMU_GBPA.
reset_value_of_SMMU_S_GBPA uint32_t 0x0-0xFFFFffff 0 Reset value of SMMU_S_GBPA.
seed uint32_t 0x0-0xFFFFffff 0x12345678 Used to seed the pseudo-random number generator that the SMMU model uses.
separate_tw_msi_qs_port bool true, false true True if there is a separate port that is used to walk configuration tables, translation tables, issue MSIs and access the queues. If this is false then pvbus_m[0] will be used.
size_of_cd_cache uint32_t 0x0-0xFFFFffff 0 The number of entries in the cache holding CD structures. If this is zero then it is treated as a large number ('infinite') but it is bounded so that the host memory usage of the cache is also bounded.
size_of_l1cd_cache uint32_t 0x0-0xFFFFffff 0 The number of entries in the cache holding L1CD descriptors. If this is zero then it is treated as a large number ('infinite') but it is bounded so that the host memory usage of the cache is also bounded.
size_of_l1ste_cache uint32_t 0x0-0xFFFFffff 0 The number of entries in the cache holding L1STE descriptors. If this is zero then it is treated as a large number ('infinite') but it is bounded so that the host memory usage of the cache is also bounded.
size_of_register_file uint64_t 0x0-0xFFFFffffFFFFffff 0x100000

This is the power of two size that the register file occupies in the memory map. It is used to generate a mask for the addresses received on pvbus_control_s to decode the desired register offset.

The default for this parameter is 1 MiB.

size_of_ste_cache uint32_t 0x0-0xFFFFffff 0 The number of entries in the cache holding STE structures. If this is zero then it is treated as a large number ('infinite') but it is bounded so that the host memory usage of the cache is also bounded.
size_of_tlb uint32_t 0x0-0xFFFFffff 0 The number of entries in the TLB. If this is zero then it is treated as a large number ('infinite') but it is bounded so that the host memory usage of the cache is also bounded.
smmu_msi_device_id uint32_t 0x0-0xFFFFffff 0 When appropriately enabled, assume that MSIs that are generated by the SMMU are presented to the GIC with this DeviceID. See parameter msi_attribute_transform and enable_device_id_checks.
support_for_httu_when_starts_disallowed unsigned 0x0-0x2 0

SMMU_IDR0.HTTU describes to the programmer whether the SMMU and system support HTTU. Typically an SMMU that is capable of HTTU will have a configuration pin that says whether the system supports HTTU or not.

The SMMU model determines SMMU_IDR0.HTTU as follows:

  • If the parameter SMMU_IDR0 indicates any kind of support for HTTU, then the configuration pin turns support on and off between that value and no support for HTTU.
  • If the parameter SMMU_IDR0 indicates no HTTU support, allow the pin to turn on support to that specified by this parameter.

Values for this parameter are the same as for the SMMU_IDR0.HTTU field:

  • 0 - no support for HTTU
  • 1 - AF flag only
  • 2 - AF flag and DBM update.
tlb_when_do_f_tlb_conflict_on_overlap int 0-2 0x0

If a TLB entry is created by a walk and it overlaps an existing entry, then there are some architectural situations where the result is known. For all others, then an implementation is allowed to use an UNPREDICTABLE combination of the two entries, or it can generate F_TLB_CONFLICT:

  • 0 -- never generate
  • 1 -- sometimes generate
  • 2 -- always generate

Conflicts between global and non-global entries are not detected by the model.

translated_device_id_base uint32_t 0x0-0xFFFFffff 0

When appropriately enabled, assume that client device accesses are translated to a DeviceID as seen by the GIC of:

StreamID + translated_device_id_base

See parameter output_attribute_transform and enable_device_id_checks.

treat_debug_read_accesses_as_speculative_accesses bool true, false false

The SMMU architecture has the concept of speculative accesses. If you set this flag to true, then debug read accesses flowing from the upstream system through the SMMU will be interpreted as speculative. The difference is that a speculative read will:

  • participate in HTTU
  • if it encounters a (non-HTTU) fault will always return abort

Debug writes are still considered as debug accesses. All speculative writes would be aborted and this is not a useful behavior for the SMMU to emulate.

unpred_httu_percent_do_discretionary_AF unsigned 0-100 50 If a descriptor could have a discretionary update of the AF flag then what is the percentage of the time that the AF update should occur.
unpred_httu_percent_do_discretionary_DBM unsigned 0-100 50 If a descriptor could have a discretionary DBM update to make the descriptor WriteableDirty then what is the percentage of the time that the DBM update should occur.
unpred_translated_access_out_of_range_of_oas unsigned 0-1 1

If a Translated Access is presented to the SMMU that is > OAS then it is constrained unpredictable as to whether the transaction will either:

  • 0 - be truncated to OAS and go downstream
  • 1 - be aborted, no event written.
wait_atos_ticks uint64_t 0x0-0x1FFFFffff 0 This is the time to wait before doing an ATOS operation. If bit 32 is set (0x1_0000_0000) then the time waited for is a uniform randomly distributed time [0,max(2,(t & 0xFFFFffff))).
wait_cmdq_ticks uint64_t 0x0-0x1FFFFffff 0 This is the time to wait before doing something on the command queue. If bit 32 is set (0x1_0000_0000) then the time waited for is a uniform randomly distributed time [0,max(2,(t & 0xFFFFffff))).
wait_eventq_ticks uint64_t 0x0-0x1FFFFffff 0 This is the time to wait before doing something on the event queue. If bit 32 is set (0x1_0000_0000) then the time waited for is a uniform randomly distributed time [0,max(2,(t & 0xFFFFffff))).
wait_msi_ticks uint64_t 0x0-0x1FFFFffff 0 This is the time to wait before sending an MSI. If bit 32 is set (0x1_0000_0000) then the time waited for is a uniform randomly distributed time [0,max(2,(t & 0xFFFFffff))).
wait_pri_req_ticks uint64_t 0x0-0x1FFFFffff 0 This is the time to wait before processing a PRI Request. If bit 32 is set (0x1_0000_0000) then the time waited for is a uniform randomly distributed time [0,max(2,(t & 0xFFFFffff))).
wait_pri_resp_ticks uint64_t 0x1-0x1FFFFffff 1 This is the time to wait before sending a PRI Response back to the PCIe subsystem. When a PRI Response is an auto-response then the ATC might immediately make a new ATS request, that immediately fails, that immediately makes a PRI Request, that auto-responds, etc. To break this loop, then we introduce a minimum time on all PRI Responses to give other components in the system a chance to run. If bit 32 is set (0x1_0000_0000) then the time waited for is a uniform randomly distributed time [0,max(2,(t & 0xFFFFffff))).
width_of_agbpa_impdef uint32_t 0-32 16 Width of the SMMU_s_AGBPA.IMPDEF field.
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