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TZIC component

This section describes the TZIC component.

TZIC - about

This LISA+ component is a model of r0p0 of the ARM® AMBA® 3 TrustZone® Interrupt Controller (SP890).

TZIC contains the following CADI targets:

  • TZIC

TZIC contains the following MTI components:

The TZIC provides a software interface to the secure interrupt system in a TrustZone design. It provides secure control of the nFIQ and masks out the interrupt sources chosen for nFIQ from the interrupts that are passed onto a non-secure interrupt controller.

TZIC - ports

This section describes the ports.

Table 4-206 TZIC ports

Name Protocol Type Description
nsfiq_in Signal Slave Connects to the nFIQ output of the non-secure interrupt controller
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
sfiq_in Signal Slave Daisy chaining secure FIQ input, otherwise connects to logic 1 if interrupt controller not daisy chained
input[32] Signal Slave 32 interrupt input sources
fiq_out Signal Master FIQ interrupt to processor
irq_out[32] Signal Master 32 IRQ output ports

TZIC - registers

This section describes the registers.

Table 4-207 TZIC registers

Name Offset Access Description
FIQStatus 0x000 Read only Provide the status of the interrupts after FIQ masking.
RawIntr 0x004 Read only Provide the status of the source interrupts and software interrupts to the interrupt controller.
IntSelect 0x008 Read/write Select whether the corresponding input source can be used to generate an FIQ or whether it passes through to TZICIRQOUT.
FIQEnable 0x00C Read/write Enable the corresponding FIQ-selected input source, which can then generate an FIQ.
FIQEnClear 0x010 Write only Clear bits in the TZICFIQEnable register.
Bypass 0x014 Read/write Enable nNSFIQIN to be routed directly to FAQ, bypassing all TZIC logic. Only the least significant bit is used.
Protection 0x018 Read/write Enable or disable protected register access, stopping register accesses when the processor is in user mode.
Lock 0x01C Write only Enable or disable all other register write access.
LockStatus 0x020 Read only Provide the lock status of the TZIC registers.

TZIC - verification and testing

This component passes tests separately using its own test suite.

This component passes tests inside the SMLT component. The FIQ passes tests under the secure environment.

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