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TarmacTrace file format

This section describes the TarmacTrace file format.

Note

[X|Y]
Indicates a choice between X and Y.
{X}
Indicates that X is optional or configuration dependent.

The common address definition that is used in the trace command syntax:

<vaddr>{:<paddr><psecurity>}
<vaddr>
The virtual address in hexadecimal format.
<paddr>
The physical address of the instruction, if available, in hexadecimal.
<psecurity>
Append _NS if the security regime of the physical address is Non-secure. Append nothing if the regime is Secure.

The virtual regime definition that is used in the trace command syntax:

0x<vbase>{_NS} <el>{ vmid=<vmid>}{, nG asid=<asid>}
0x<vbase>
Virtual address in hexadecimal format.
_NS
If present, this element specifies that the address is Non-secure. If not present, the address is Secure.
<el>

Translation regime that owns the mapping. One of:

  • EL1_n, meaning the Non-secure EL1&0 translation regime.
  • EL2_n
  • EL1_s
  • EL3_s
<vmid>
For Non-secure, non-hyp regimes, specify the VMID.
nG
If present, this element specifies that the virtual regime is non-global.
asid
For non-global regimes, specify the ASID.

Instruction trace

If enabled, this trace source generates one record for every instruction started.

The records (lines) of the instruction trace have this syntax:

<time> <scale> <cpu> [IT|IS] (<inst_id>) <addr> <opcode> [A|T|X|O] <mode>_<security> : <disasm>

<time>

Timestamp (decimal value).

<scale>

Unit for <time>. clk indicates that the timestamp is not related to real time, but an increasing count.

<cpu>

Processor, or other component, that gave the instruction.

[IT|IS]
IT
Instruction passed the condition code (taken).
IS
Instruction failed the condition code (skipped).
<inst_id>

Tick count of this processor, which is equivalent to the number of instructions that are executed, except for certain instructions like WFI/WFE (decimal value).

<addr>

Fetch source address for this instruction. Format according to the common address definition.

<opcode>

16-bit/32-bit hexadecimal opcode of the instruction.

[A|T|X|O]

Instruction set:

A
A32.
T
T32.
X
T32EE.
O
A64
<mode>

Processor execution mode.

AArch32 modes are svc, irq, fiq, usr, mon, sys, abt, und, hyp.

AArch64 modes are EL3h, EL3t, EL2h, EL2t, EL1h, EL1t, EL0t.

<security>

Processor security state (s or ns).

<disasm>

Disassembly of the instruction.

Program flow trace

If enabled, every executed branch instruction triggers this trace source, which is a more efficient way to reconstruct the program flow than by tracing every instruction.

Output syntax:

<time> <scale> {<cpu>} [FD|FI] (<inst_id>) <addr> <targ_addr> [A|T|X|O]

<time>

Timestamp (decimal value).

<scale>

Unit for <time>. Gives consistency with device-specific Tarmac Trace formats.

<cpu>

Processor, or other component, that gave the instruction.

[FD|FI]

Program flow change by:

FD
A direct branch.
FI
An indirect branch.
<inst_id>

Tick count of this processor, which is equivalent to the number of instructions that are executed, except for certain instructions like WFI/WFE (decimal value).

<addr>

Fetch source address for this instruction. Format according to the common address definition.

<targ_addr>

Address (virtual) at which the execution continues. Format according to the common address definition.

[A|T|X|O]

Instruction set after the branch:

A
A32.
T
T32.
X
T32EE.
O
A64

Register trace

If enabled, this source traces all writes to the processor registers.

This trace source includes writes to core registers R0 to R14, X0 to X30, CPSR, and SPSR, VFP registers such as S0 to S31, D0 to D31, FPSCR, and FPEXC, and writes to system registers including CP14, CP15, and GIC. Banked registers are traced separately using the mode as a suffix to the register name, for example r13 (current register R13) and r13_mon (banked register R13).

Output syntax:

<time> <scale> {<cpu>} R <register> <value>

<time>

Timestamp (decimal value).

<scale>

Unit for <time>, which gives consistency with device-specific Tarmac Trace formats.

<cpu>

Processor, or other component, that gave the instruction.

<register>

Register name in lowercase letters. Banked core registers can have a mode appended to them with a single underscore. Banked CP14/CP15 registers have _s or _ns appended to indicate access of either the Secure or Non-secure banked register.

<value>

Hexadecimal value that is written to the register (64 bits maximum).

If the SVE plug-in is loaded in the model, there are additional registers in the program view. The output examples below show how these registers are traced when the value changes. These data values can be very large.

clk cpu0 IT (8439) 000282c0:0000152282c0_NS 053fc01f O EL1h_n : SEL      z31.B,p0,z0.B,z31.B
8463 clk cpu0 R z31 00000000_00000000_00000000_00000000

R indicates a register write. z0 to z31 are the vector registers. The written data are hexadecimal digits, which are separated by an underscore every 32 bits. The length of the written data varies with the configuration, depending on the vector length.

clk cpu0 IT (9732) 01000074:000011000074_NS 2518e3e0 O EL1t_n : PTRUE    p0.B,ALL
9756 clk cpu0 R p0 ffff

R indicates a register write. p0 to p15 are the predicate registers. The written data are hexadecimal digits. If they are long enough to require one, the digits are separated by an underscore every 32 bits. The length of the written data varies with the configuration, depending on the vector length. Predicate registers contain 1 bit per byte of vector register length.

Cache maintenance trace

If enabled, this source traces all cache maintenance operations that the processor initiates.

Output syntax:

<time> <scale> <cpu> CACHE MAINTENANCE <side> <operation> <scope> <data> {<pagesize> <memtype>}
<time>

Timestamp (decimal value).

<scale>

Unit for <time>. clk indicates that the timestamp is not related to real time, but an increasing count.

<cpu>

Processor, or other component, that gave the instruction.

<side>
Data or instruction cache.
<operation>
Clean, invalidate, or both.
<scope>
By MVA or set/way, to Point of Coherency or Point of Unification, Inner Sharable or not.
<data>
Data that is associated with the operation. If the operation is by MVA, format according to the common address definition, otherwise use raw hexadecimal.
<pagesize>
If the operation is by MVA, this element is the size of the memory region that is described by the TLB entry which contains the MVA.
<memtype>
If the operation is by MVA, this element is the type of memory in the TLB entry which contains the MVA.

Cache content trace

Traces the movement of data into and out of the cache.

Output syntax:

<time> <scale> <cpu> CACHE <id> LINE <line> <operation> 0x<paddr><ns>
<time>

Timestamp (decimal value).

<scale>

Unit for <time>. clk indicates that the timestamp is not related to real time, but an increasing count.

<cpu>

Processor, or other component, that gave the instruction.

<id>
Level and side, or system identifier, of the cache.
<line>
Identifier of this line uniquely within this cache, expressed in hexadecimal.
<operation>
Notification for this cache line. One of the following options:
ALLOC
(Processor caches) Line contains new read data.
INVAL
(Processor caches) Line contains no data.
DIRTY
(Processor caches) Line contains new write data.
CLEAN
(Processor caches) Write data is written back, still valid for reads.
FILL
(System caches) Line is filled.
EVICT
(System caches) Line is evicted due to space pressure.
CLEAN
(System caches) Line is cleaned due to maintenance operation.
INVAL
(System caches) Line is invalidated due to maintenance operation.
<paddr>
Cache line physical address in hexadecimal.
<ns>
Cacheline security. Blank for Secure regime, or _NS for Non-secure regime.

Translation table walk trace

If enabled, this source traces all translation table walks initiated by the processor

Output syntax:

<time> <scale> <cpu> [TTW|TTU] <side> <format> <stage>:<level> <address> <data> : <result>
<time>

Timestamp (decimal value).

<scale>

Unit for <time>. clk indicates that the timestamp is not related to real time, but an increasing count.

<cpu>

Processor, or other component, that gave the instruction.

[TTW|TTU]
Translation table walks (reads) or translation table update (writes).
<side>
Data or instruction TLB.
<format>
VMSA or LPAE format translation table entries.
<stage>
Walk stage, within the range 1-2.
<level>
Walk level, within the range 1-3.
<address>
Physical address of lookup in hexadecimal.
<data>
Raw translation table entry in hexadecimal.
<result>
Parsed result. One of the following options:
ABORTED
The memory access caused a synchronous abort and no data was returned.
FAULT
The data that was returned is not valid for this stage and level.
RESERVED
The data that was returned is not valid for this stage and level.
TABLE {<attr>=<value>}+
Pointer to the next level of lookup, in LPAE format.
BLOCK {<attr>=<value>}
LPAE region descriptor.
SUPERSECTION {<attr>=<value>}
VMSA region descriptor.
SECTION {<attr>=<value>}
VMSA region descriptor.
PAGETABLE {<attr>=<value>}
Pointer to the next level of lookup, in VMSA format.
LARGEPAGE {<attr>=<value>}
VMSA region descriptor.
SMALLPAGE {<attr>=<value>}
VMSA region descriptor.

TLB trace

If enabled, this source traces TLB entries that are filled and evicted by the processor.

Output syntax:

<time> <scale> <cpu> [TLB|WALKCACHE] FILL <id> <size> <virtualregime>:<paddr> {<memtype>} {<attr>=<value>}+
<time> <scale> <cpu> [TLB|WALKCACHE] EVICT <id> <size> <virtualregime>
<time>

Timestamp (decimal value).

<scale>

Unit for <time>. clk indicates that the timestamp is not related to real time, but an increasing count.

<cpu>

Processor, or other component, that gave the instruction.

<id>
Identifies which TLB or walk cache to trace.
<size>
Size of the region being mapped.
<virtualregime>
Virtual address and regime of the region being mapped, formatted according to the common virtual regime definition.
<paddr>
Physical base address of mapped region, formatted according to the common address definition.
<memtype>
For TLB entries, the memory type of the result. One of the following options:
Device-[G|nG][R|nR][E|nE] {(<alias>)}
Device memory, where:
[G|nG]
Gathering or nongathering.
[R|nR]
Reordering or nonreordering.
[E|nE]
Early write acknowledgement or not.
<alias>
Device-nGnRnE was previously known as StronglyOrdered.
Normal [NonShareable|Shareable] Inner=<cachetype> Outer=<cachetype>
Normal memory, where:
[NonShareable|Shareable]
Shareability
<cachetype>
[NonCacheable|WriteBack|WriteThrough]{NonReadAllocate}{Non}{WriteAllocate}
[NonCacheable|WriteBack|WriteThrough]
Cacheability
{NonReadAllocate}
For cacheable memory, Read allocate hint. (Read allocate is assumed if not specified.)
{Non}{WriteAllocate}
For cacheable memory, Write allocate hint.

Event trace

If enabled, this source traces exceptions and interrupts occurring.

Output syntax:

<time> <scale> {<cpu>} E <value> {<mode>} {<value1>} <number> <desc>

<time>

Timestamp (decimal value).

<scale>

Unit for <time>, which gives consistency with device-specific Tarmac Trace formats.

<cpu>

Processor, or other component, that gave the instruction.

<value>

A value that is associated with the event. Format according to the common address definition.

<mode>
For mode change events only, the new mode being entered.
<value1>
Where available, the hexadecimal representation of a second value that is associated with the event.
<number>

Event number.

<desc>

Event name.

Table 6-16 Supported values for value, number, and desc

Number

Event description

Value

00000001

CoreEvent_Reset

-

00000002

CoreEvent_UndefinedInstr

-

00000003

CoreEvent_SWI

SWI number

00000004

CoreEvent_PrefetchAbort

-

00000005

CoreEvent_DataAbort

-

00000007

CoreEvent_IRQ

-

00000008

CoreEvent_FIQ

-

0000000E

CoreEvent_ImpDataAbort

-

00000019

CoreEvent_ModeChange

New mode

00000080

CoreEvent_CURRENT_SP0_SYNC

-

00000088

CoreEvent_LOWER_64_SYNC

-

Processor memory access trace

If enabled, this source traces processor data accesses.

Output syntax:

<time> <scale> {<cpu>} M<rw><sz><attrib> <addr> <data>

<time>

Timestamp (decimal value).

<scale>

Unit for <time>. This element gives consistency with device-specific Tarmac Trace formats.

<cpu>

Processor, or other component, that gave the instruction.

<rw>
R
Read access.
W
Write access.
<sz>

Size of the data transfer in bytes (1, 2, 4, 8).

<attrib>

Optional access attribute:

X
Exclusive access.
T
Translated (unprivileged) access.
L
Locked access (SWP, SWPB instructions).
<addr>

Virtual address that is used to access memory. Format according to the common address definition.

<data>

Hexadecimal value of data transferred. The data padding is according to the size of the transfer. Data of 64 bits or more contains an underscore (_) separator every eight characters (32 bits).

Processor memory update trace

If enabled, this source traces memory update accesses caused by atomic operations.

Output syntax:

<time> <scale> {<cpu>} MU<sz>_<atomic_op> <addr> <data>

<time>

Timestamp (decimal value).

<scale>

Unit for <time>. This element gives consistency with device-specific Tarmac Trace formats.

<cpu>

Processor, or other component, that gave the instruction.

<sz>

Size of the data transfer in bytes (1, 2, 4, 8, 16).

<atomic_op>

Atomic operation performed on this memory address:

ADD
Atomic add operation.
BIC
Atomic bit clear operation.
CAS
Atomic compare and swap operation.
EOR
Atomic exclusive or operation.
ORR
Atomic bit set operation.
SMAX
Atomic signed max operation.
SMIN
Atomic signed min operation.
SWP
Atomic swap operation.
UMAX
Atomic unsigned max operation.
UMIN
Atomic unsigned min operation.
<addr>

Physical address that is used to access memory. Format according to the common address definition.

<data>

Hexadecimal value of the data transferred. The data padding is according to the size of the transfer. Data of 64 bits or more contains an underscore (_) separator every eight characters (32 bits).

Memory bus trace

If enabled, this source traces transactions that are initiated through the memory bus master port of the processor. These accesses use physical addresses.

Output syntax:

<time> <scale> {<cpu>} B<rw><sz><fd><lk><p><s> I<wrcbs> O<wrcbs> <master_id> <addr> <data>

<time>

Timestamp (decimal value).

<scale>

Unit for <time>. This element gives consistency with device-specific Tarmac Trace formats.

<cpu>

Processor, or other component, that gave the instruction.

<rw>
R
Read access.
W
Write access.
<sz>

Size of the data transfer in bytes.

<fd>
I
Opcode fetch.
D
Data load/store or an MMU access.
<lk>
L
Locked access.
X
Exclusive access.
_, underscore
Normal access.
<p>
P
Privileged access.
_, underscore
Normal access.
<s>
S
Secure access.
N
Non-secure access.
I<wrcbs>

Inner cache attributes. See O<wrcbs>.

O<wrcbs>

Outer cache attributes:

<w>
W
Allocate on write.
_, underscore
No allocate on write.
<r>
R
Allocate on read.
_, underscore
No allocate on read.
<c>
C
Cacheable access.
_, underscore
Non-cacheable access.
<b>
B
Bufferable access.
_, underscore
Non-bufferable access.
<s>
S
Shareability access.
_, underscore
Non-shareability access.
<master_id>

Master ID of the transaction.

<addr>

Physical address that is used to access memory, in hexadecimal format.

<data>

Hexadecimal value of data transferred. The data padding is according to the size of the transfer. Byte ordering is from lowest to highest byte. This ordering means that for accesses in little endian mode, the data occurs mirrored compared to the register/memory access records.

Tarmac Trace output example

This is an example of a trace that was produced by the Tarmac Trace plug-in, showing instruction, register, event, and memory access traces.

1939 clk cpu0 IT (1915) 0001129c:00001521129c d51bd061 O EL3h_s : MSR TPIDRRO_EL0,x1
1939 clk cpu0 R TPIDRRO_EL0 00000000:00000000
1940 clk cpu0 IT (1916) 000112a0:0000152112a0 d001c100 O EL3h_s : ADRP x0,{pc}+0x3822000 ; 0x38332a0
1940 clk cpu0 R X0 0000000003833000
1941 clk cpu0 IT (1917) 000112a4:0000152112a4 91024000 O EL3h_s : ADD x0,x0,#0x90
1941 clk cpu0 R X0 0000000003833090
1942 clk cpu0 IT (1918) 000112a8:0000152112a8 d2810002 O EL3h_s : MOV x2,#0x800
1942 clk cpu0 R X2 0000000000000800
1943 clk cpu0 IT (1919) 000112ac:0000152112ac 91000421 O EL3h_s : ADD x1,x1,#1
1943 clk cpu0 R X1 0000000000000001
1944 clk cpu0 IT (1920) 000112b0:0000152112b0 9b017c42 O EL3h_s : MUL x2,x2,x1
1944 clk cpu0 R X2 0000000000000800
1945 clk cpu0 IT (1921) 000112b4:0000152112b4 8b020000 O EL3h_s : ADD x0,x0,x2
1945 clk cpu0 R X0 0000000003833890
1946 clk cpu0 IT (1922) 000112b8:0000152112b8 9100001f O EL3h_s : MOV sp,x0
1946 clk cpu0 R SP_EL3 0000000003833890
1947 clk cpu0 IT (1923) 000112bc:0000152112bc 10001420 O EL3h_s : ADR x0,{pc}+0x284 ; 0x11540
1947 clk cpu0 R X0 0000000000011540
1947 clk cpu0 CACHE cpu.cpu0.l1icache LINE 0096 ALLOC 0x0000152112c0
1947 clk cpu0 CACHE Validation_ARMAEMv8AMPCT.cpu.l2_cache LINE 04b0 ALLOC 0x0000152112c0
1948 clk cpu0 IT (1924) 000112c0:0000152112c0 f9400000 O EL3h_s : LDR x0,[x0,#0]
1948 clk cpu0 MR8 00011540:000015211540 00000000_13000000
1948 clk cpu0 R X0 0000000013000000
1948 clk cpu0 CACHE cpu.cpu0.l1dcache LINE 00aa ALLOC 0x000015211540
1948 clk cpu0 CACHE Validation_ARMAEMv8AMPCT.cpu.l2_cache LINE 0550 ALLOC 0x000015211540
1949 clk cpu0 IT (1925) 000112c4:0000152112c4 d0000081 O EL3h_s : ADRP x1,{pc}+0x12000 ; 0x232c4
1949 clk cpu0 R X1 0000000000023000
1950 clk cpu0 IT (1926) 000112c8:0000152112c8 91017021 O EL3h_s : ADD x1,x1,#0x5c
1950 clk cpu0 R X1 000000000002305C
1951 clk cpu0 IT (1927) 000112cc:0000152112cc d63f0020 O EL3h_s : BLR x1
1951 clk cpu0 R X30 00000000000112D0
1951 clk cpu0 TTW ITLB LPAE 1:3 000016390010 00000000152204c3 : BLOCK ATTRIDX=0 NS=0 AP=3 SH=0 AF=1 nG=0 16E=0 PXN=0 XN=0 ADDR=0x0000000015220000
1951 clk cpu0 TLB FILL cpu.cpu0.ITLB 64K 0x00020000, nG asid=0:0x0015220000 Normal NonShareable Inner=WriteBackWriteAllocate Outer=WriteBackWriteAllocate xn=0 pxn=0 ContiguousHint =0
1951 clk cpu0 TLB FILL cpu.cpu0.S1TLB 64K 0x00020000, nG asid=0:0x0015220000 Normal NonShareable Inner=WriteBackWriteAllocate Outer=WriteBackWriteAllocate xn=0 pxn=0 ContiguousHint =0
1951 clk cpu0 CACHE cpu.cpu0.l1icache LINE 0182 ALLOC 0x000015223040
1951 clk cpu0 CACHE Validation_ARMAEMv8AMPCT.cpu.l2_cache LINE 0c10 ALLOC 0x000015223040
1952 clk cpu0 IT (1928) 0002305c:00001522305c f0030f48 O EL3h_s : ADRP x8,{pc}+0x61eb000 ; 0x620e05c
1952 clk cpu0 R X8 000000000620E000
1953 clk cpu0 IT (1929) 00023060:000015223060 f9000100 O EL3h_s : STR x0,[x8,#0]
1953 clk cpu0 TTW DTLB LPAE 1:3 000016393100 0000000016000463 : BLOCK ATTRIDX=0 NS=1 AP=1 SH=0 AF=1 nG=0 16E=0 PXN=0 XN=0 ADDR=0x0000000016000000
1953 clk cpu0 MW8 0620e000:00001600e000_NS 00000000_13000000
1953 clk cpu0 TLB FILL cpu.cpu0.DTLB 64K 0x06200000, nG asid=0:0x0016000000_NS Normal NonShareable Inner=WriteBackWriteAllocate Outer=WriteBackWriteAllocate xn=0 pxn=0 ContiguousHint =0
1953 clk cpu0 TLB FILL cpu.cpu0.S1TLB 64K 0x06200000, nG asid=0:0x0016000000_NS Normal NonShareable Inner=WriteBackWriteAllocate Outer=WriteBackWriteAllocate xn=0 pxn=0 ContiguousHint =0
1953 clk cpu0 CACHE cpu.cpu0.l1dcache LINE 0188 ALLOC 0x000016393100
1953 clk cpu0 CACHE Validation_ARMAEMv8AMPCT.cpu.l2_cache LINE 0c40 ALLOC 0x000016393100
1954 clk cpu0 IT (1930) 00023064:000015223064 17fffff5 O EL3h_s : B {pc}-0x2c ; 0x23038
1954 clk cpu0 CACHE cpu.cpu0.l1icache LINE 0180 ALLOC 0x000015223000
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