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ARM_Cortex-A55 - trace

This section describes the trace sources.

ASYNC_MEMORY_FAULT

Context ID Register write. Fields:

FAULT unsigned int: Fault status in ESR format
PADDR unsigned int: Physical Address (or 0 if unavailable)
VADDR signed int: Virtual Address (or 0 if unavailable)

ATOMIC_END_ACCESS

Bus trace access for atomics. Fields:

ACCESS_FAIL bool: Memory access failed
ADDR unsigned int: The virtual address of the access.
ATTR unsigned int: Transaction Attributes: [12] instruction fetch [11] non_secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable). All other bits are implementation defined
COMPARE_VALUE unsigned int: Compare value for CAS
LOAD_VALUE unsigned int: Loaded values
NSDESC unsigned int: The security state of the access.
OPERAND_VALUE unsigned int: Operation's operand
OPERATION enum: Operation type
PADDR unsigned int: The physical address of the access.
PRIV bool: Is this a privileged access?

ATOMIC_START_ACCESS

Bus trace access for atomics. Fields:

ADDR unsigned int: The virtual address of the access.
ATTR unsigned int: Transaction Attributes: [12] instruction fetch [11] non_secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable). All other bits are implementation defined
COMPARE_VALUE unsigned int: Compare value for CAS
NSDESC unsigned int: The security state of the access.
OPERAND_VALUE unsigned int: Operation's operand
OPERATION enum: Operation type
PADDR unsigned int: The physical address of the access.
PRIV bool: Is this a privileged access?

ArchMsg.Warning.RAS_ErrselrUnpredictableState

ERRSELR is in unpredictable state due to value greater than number_of_error_records written to it.

ArchMsg.Warning.RAS_UnpredictableStateWrite

Fields:

REG_NAME string: Name of register being written.

ArchMsg.Warning.Unpredictably Indexed PM Event Register

Fields:

IsDirect unsigned int: Direct Access rather than indirect
N unsigned int: Number of Accessible Registers
SEL unsigned int: Selector

ArchMsg.Warning.branch_to_unaligned_address

Fields:

ADDR unsigned int: Unaligned branch address

ArchMsg.Warning.cache_contents_unknown

A cache has been activated without being invalidated and may contain UNKNOWN content. Fields:

REGIME unsigned int: Current translation regime
SIDE unsigned int: 0 d-side cache or unified cache, 1 i-side

ArchMsg.Warning.dcimvac_matches_watchpoint

Watchpoints matching an AArch32 DCIMVA are implementation defined.

ArchMsg.Warning.decode_fieldmismatch

Fields:

FIELD1 enum: Field name
FIELD2 enum: Field name

ArchMsg.Warning.decode_fracbitsnegative

VCVT Instruction is unpredictable with a negative number of fraction bits.

ArchMsg.Warning.decode_initblock

Instruction is unpredictable in an IT block.

ArchMsg.Warning.decode_initblocknotlast

Instruction is unpredictable in an IT block when not the last.

ArchMsg.Warning.decode_invalid_condition

Instruction is unpredictable when the condition is not AL.

ArchMsg.Warning.decode_invalidfieldcombination

Fields:

FIELD1 enum: Field name
FIELD2 enum: Field name

ArchMsg.Warning.decode_invalidvalue

Fields:

FIELD enum: Field name

ArchMsg.Warning.decode_mem_hint_unallocated

There is no memory hint allocated to this bit pattern.

ArchMsg.Warning.decode_registermatch

Fields:

FIELD1 enum: Field name
FIELD2 enum: Field name

ArchMsg.Warning.decode_registermismatch

Fields:

FIELD1 enum: Field name
FIELD2 enum: Field name

ArchMsg.Warning.decode_registeroutofrange

Float point instruction is unpredictable indexing beyond the end of the register bank.

ArchMsg.Warning.decode_sbzsbo

Reserved bits in the instruction are not canonical.

ArchMsg.Warning.decode_transactiontoobig

Attempt to perform a memory transaction of more than 128 bytes.

ArchMsg.Warning.decode_unpred_other

Instruction is unpredictable.

ArchMsg.Warning.decode_unpreduseofpc

Fields:

FIELD enum: Field name

ArchMsg.Warning.decode_unpreduseofr13

Fields:

FIELD enum: Field name

ArchMsg.Warning.decode_unpreduseofr13inreglist

Instruction is unpredictable with R13 in register-list.

ArchMsg.Warning.decode_writebackandbaseinlist

Instruction is unpredictable with write back when the base register is in the transfer list.

ArchMsg.Warning.decode_zeroregistersinlist

Instruction is unpredictable when no registers are to be transfered.

ArchMsg.Warning.recursive_branch

An instruction is performing a branch that targets the same instruction. If this was intended then a WFI might be more effective. Fields:

PC unsigned int: Address of instruction causing the branch

ArchMsg.Warning.recursive_exception

An instruction has generated an exception that targets the same instruction. Fields:

CPSR unsigned int: Processor state
PC unsigned int: Address of instruction causing the exception
TYPE enum: Type of exception

ArchMsg.Warning.reentrant_vector_catch

Fields:

ADDR unsigned int: vector address

ArchMsg.Warning.reserved_it_state

Fields:

ITSTATE unsigned int: reserved IT state

ArchMsg.Warning.tlb_contents_unknown

Translation has been enabled without invalidating the TLB. Fields:

INVALIDITY unsigned int: Which TLB may be invalid (if TLBs are separate)
REGIME unsigned int: Current translation regime
VMID unsigned int: Current VMID if applicable

ArchMsg.Warning.unknown_DLR_DSPSR

Exiting debug state with unknown DLR or DSPSR.

ArchMsg.Warning.unknown_ELR_SPSR

Returning from debug exception with unknown ELR or SPSR.

ArchMsg.Warning.unpredictable_a32_breakpoint

Fields:

ADDR1 unsigned int: Address
ADDR2 unsigned int: Breakpoint address
BAS unsigned int: BAS Field
IS_ADDRESS_MISMATCH_BREAKPOINT bool: Is Mismatch breakpoint, not a match breakpoint
N unsigned int: Breakpoint number
OFFSET unsigned int: Indicates which halfword actually considering into the A32 instruction

ArchMsg.Warning.unpredictable_banked_register_access

Fields:

R unsigned int: R bit
SYSM unsigned int: SYSm

ArchMsg.Warning.unpredictable_ccfail_undef

Fields:

OPCODE unsigned int: opcode of the instruction
VADDR unsigned int: Virtual address of the instruction being executed

ArchMsg.Warning.unpredictable_ici_bits

ICI bits do not apply or are architecturally unpredictable for instruction.

ArchMsg.Warning.unpredictable_t32_breakpoint

Fields:

ADDR1 unsigned int: Address
ADDR2 unsigned int: Breakpoint address
BAS unsigned int: BAS Field
IS_ADDRESS_MISMATCH_BREAKPOINT bool: Is Mismatch breakpoint, not a match breakpoint
N unsigned int: Breakpoint number
OFFSET unsigned int: Indicates which halfword actually considering into the T32 instruction

ArchMsg.Warning.unpredictable_t32_vector_catch

Fields:

ADDR unsigned int: Address
OFFSET unsigned int: Indicates which halfword actually considering into the T32 instruction

ArchMsg.Warning.unpredictable_watchpoint_far

Fields:

LOWER_BOUND unsigned int: the lowest address accessed by the instruction that triggered the watchpoint
UPPER_BOUND unsigned int: the highest watchpointed address accessed by that instruction

ArchMsg.Warning.warning_AdvSIMDExpandImmUnexpectedZero

AdvSIMDExpandImm may treat this immediate value as UNPREDICTABLE.

ArchMsg.Warning.warning_ConditionalSMC

SMC instruction has UNPREDICTABLE effects when conditional when combined with traps.

ArchMsg.Warning.warning_access_crosses_page_boundary

Access crosses page boundary.

ArchMsg.Warning.warning_access_crosses_page_boundary_has_fault

Access crosses page boundary has fault(s).

ArchMsg.Warning.warning_access_crosses_page_boundary_has_fault_on_both_pages

Access crosses page boundary has fault(s).

ArchMsg.Warning.warning_access_crosses_page_boundary_spanning_different_memory

Fields:

ADDR unsigned int: address of access crossing page
MEMTYPE_PAGE1 signed int: First Page's memory type (0-Normal, 1-Non-Normal)
MEMTYPE_PAGE2 signed int: Second Page's memory type (0-Normal, 1-Non-Normal)

ArchMsg.Warning.warning_access_wraps_around_memory

Fields:

WIDTH unsigned int: Address width

ArchMsg.Warning.warning_bx_from_thumbee

Fields:

ADDR unsigned int: Destination address

ArchMsg.Warning.warning_ccsidr_unimplemented_level

Fields:

CSSELR unsigned int: current effective value of CSSELR

ArchMsg.Warning.warning_change_to_ns_when_tge_set

Attempting to change NS to 1 when HCR.TGE = 1.

ArchMsg.Warning.warning_contiguous_bit_check_abort

Fields:

ENTRY_ADDR unsigned int: address of conflicting TLB entry

ArchMsg.Warning.warning_contiguous_bit_error

Fields:

CONTIG_ADDR unsigned int: address of the TLB first read, with which this entry is expected to be contiguous
CONTIG_DATA unsigned int: expected contents based on the entry at CONTIG_ADDR
ENTRY_ADDR unsigned int: address of conflicting TLB entry
ENTRY_DATA unsigned int: contents of conflicting TLB entry

ArchMsg.Warning.warning_cp10_cp11_mismatch

Fields:

EL unsigned int: EL owning the control

ArchMsg.Warning.warning_cp10_cp11_reserved_value

Fields:

CP10 unsigned int: CP10 access
CP11 unsigned int: CP11 access

ArchMsg.Warning.warning_csselr_level_out_of_range

Fields:

DATA bool: whether the cache is a data cache
IMPLEMENTED unsigned int: number of cache levels implemented
LEVEL unsigned int: written value of CSSELR.Level

ArchMsg.Warning.warning_debug_flow_control_bits_not_obeyed

Fields:

ERROR enum: type of error resulting
REGISTER enum: register under consideration

ArchMsg.Warning.warning_debug_register_access_during_reset

Fields:

IS_WRITE unsigned int: Write Not Read
OFFSET unsigned int: Register Offset

ArchMsg.Warning.warning_decode_cps_inconsistent_fields

The mode setting fields in the CPS instruction are inconsistent.

ArchMsg.Warning.warning_decode_invalid_state

Instruction is unpredictable in current exception-level/security state.

ArchMsg.Warning.warning_default_cacheable_mmu_on

Default cacheable is enabled (HCR.DC = 1) while MMU is enabled.

ArchMsg.Warning.warning_default_cacheable_vmmu_off

Default cacheable is enabled (HCR.DC = 1) while HCR.VM = 0.

ArchMsg.Warning.warning_deprecated_wvr_bit_2_set

Fields:

N unsigned int: index
WVR unsigned int: DBGWVR

ArchMsg.Warning.warning_eret_while_software_step_active_pending

Missing ISB between setting MDSCR_EL1.SS and ERET.

ArchMsg.Warning.warning_exclusive_to_non_normal

Fields:

ADDR unsigned int: Address

ArchMsg.Warning.warning_exclusive_to_non_writeback

Fields:

ADDR unsigned int: Address

ArchMsg.Warning.warning_execute_from_device_memory

An attempt was made to execute from Device memory.

ArchMsg.Warning.warning_illegal_cpsr_mode

Fields:

NEW_MODE unsigned int: New value of CPSR.M

ArchMsg.Warning.warning_illegal_srs_mode

Fields:

MODE unsigned int: mode for Banked SP

ArchMsg.Warning.warning_implementation_defined_read_debug_register_in_SCS

Read Access to Debug registers from the processor is IMPLEMENTATION DEFINED. Fields:

PPB_OFFSET unsigned int: debug register offset

ArchMsg.Warning.warning_implementation_defined_sequential_security_transitions_supported

The behaviour of a sequential instruction fetches that cross from non-secure to secure memory and contain SG instruction is CONSTRAINED UNPREDICTABLE.

ArchMsg.Warning.warning_implementation_defined_stack_limit_check_supported

It is IMPLEMENTATION DEFINED whether stack pointer limit checking is performed for the this instructions. Fields:

ADDRESS unsigned int: Address of instruction
OPCODE unsigned int: instruction opcode

ArchMsg.Warning.warning_implementation_defined_write_debug_register_in_SCS

Write Access to Debug registers from the processor is IMPLEMENTATION DEFINED. Fields:

DATA unsigned int: data attempted to be written
PPB_OFFSET unsigned int: debug register offset

ArchMsg.Warning.warning_invalid_tcr_granule

Fields:

REQUEST signed int: page size requested (or 0 for reserved)
SUBSTITUTE signed int: best guess available page size
TG_ID bool: bits TG0 or TG1

ArchMsg.Warning.warning_load_multiple_user_registers_from_user_mode

An LDM(user registers) instruction executed from user mode.

ArchMsg.Warning.warning_load_pc_from_unaligned

PC loaded from an unaligned location.

ArchMsg.Warning.warning_reserved_breakpoint_state_match

Fields:

IS_BREAKPOINT unsigned int: Is breakpoint, not watchpoint

ArchMsg.Warning.warning_shareability

Unpredictable: combination of the 1st and 2nd stages of translation is Normal Inner Non-Cacheable, Outer Non-Cacheable.

ArchMsg.Warning.warning_software_step_set_while_enabled

MDSCR_EL1.SS set to 1 while software step debug exceptions are enabled.

ArchMsg.Warning.warning_thumb_instruction_wraps_around_memory

Thumb instruction warps around memory.

ArchMsg.Warning.warning_ttbr_sbz_bits_are_not_zero

Fields:

MSB unsigned int: x-1
TTBR enum: which TTBR register

ArchMsg.Warning.warning_unaligned_address_dbgdtrrx_write

Fields:

ADDR unsigned int: Address

ArchMsg.Warning.warning_unaligned_address_dbgdtrtx_read

Fields:

ADDR unsigned int: Address

ArchMsg.Warning.warning_unaligned_to_device

Fields:

ADDR unsigned int: Address

ArchMsg.Warning.warning_unaligned_to_strongly_ordered

Fields:

ADDR unsigned int: Address

ArchMsg.Warning.warning_unknown_sau_rnr

SAU_RNR was set to an unsupported value.

ArchMsg.Warning.warning_unpredictable_AIRCR_PRIP_and_BFHFNMINP

The effect of setting both AIRCR.BFHFNMINP and AIRCR.PRIP to 1 is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_AIRCR_VECTCLRACTIVE_when_not_in_debug

The effect of writing a 1 to AIRCR.VECTCLRACTIVE if the processor is not halted in Debug state is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_AIRCR_VECTRESET_and_SYSRESETREQ

When the processor is halted in Debug state, if a write to the register writes a 1 to both VECTRESET and SYSRESETREQ, the behavior is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_AIRCR_VECTRESET_when_not_in_debug

The effect of writing a 1 to AIRCR.VECTRESET if the processor is not halted in Debug state is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_AIRCR_incorrect_VKEY

The value 0x05FA must be written to AIRCR.VKEY, otherwise the register write is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_EXE_RETURN_Reserved_Bit

EXC_RETURN[23:7] are reserved with the special condition that all bits should be written as one. Values other than all 1s are UNPREDICTABLE. Fields:

EXC_RETURN unsigned int: Special PC value
SBO_MASK unsigned int: Which bits Should Be One to not UNPRED

ArchMsg.Warning.warning_unpredictable_change_to_DEMCR_MON_STEP_at_insufficient_priority

The effect of changing DEMCR.MON_STEP at an execution priority that is lower than the priority of the DebugMonitor exception is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_change_to_priority_of_active_exception

Changing the priority of an active exception is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_clear_lspact

Fields:

DRVEXC_TAKEN unsigned int: derived exception taken not pended
REACHED_LAST_STORE unsigned int: only the last faulted

ArchMsg.Warning.warning_unpredictable_dbg_exit_unaligned_dlr

Debug exit to AArch32 with DLR[0] set to 1. PC[0] can be set to 0 or to DLR[0].

ArchMsg.Warning.warning_unpredictable_exception_catch

Generation of an exception catch event is unpredictable.

ArchMsg.Warning.warning_unpredictable_exception_return_inconsistent_state

state on exception return is unpredictable.

ArchMsg.Warning.warning_unpredictable_exception_return_instruction

exception return instruction is unpredictable.

ArchMsg.Warning.warning_unpredictable_in_debug_state

Instruction is UNPREDICTABLE when executed in debug state.

ArchMsg.Warning.warning_unpredictable_pmu_counter_access

Access to PMU counters from non-secure EL0 or EL1 is UNPREDICTABLE with MDCR_EL2.HPMN set to 0.

ArchMsg.Warning.warning_unpredictable_prioritization_breakpoint_match_vector_catch

Two events with the same priority occurred at the same instruction: Address Matching Vector Catch debug event, and Breakpoint debug event It is constrained unpredictable which is taken.

ArchMsg.Warning.warning_unpredictable_stack_selection

UNPREDICTABLE state on context switch.

ArchMsg.Warning.warning_unpredictable_tsize_out_of_range

Fields:

TCR enum: Which TCR
TSIZE signed int: Value of TSize
TSIZE_MAX signed int: The maximum allowed value
TTBR unsigned int: Which TTBR region

ArchMsg.Warning.warning_unpredictable_unaligned_pc_as_base_register

The PC value must be word-aligned, otherwise the behavior of the instruction is UNPREDICTABLE.

ArchMsg.Warning.warning_unpredictable_unaligned_pop_stack

Fields:

FRAME_ADDR unsigned int: unaligned stack frame address

ArchMsg.Warning.warning_unpredictable_vmsa_memattrib

Fields:

TEXCB unsigned int: texcb value
TEX_REMAP bool: use tex remap

ArchMsg.Warning.warning_unpredictable_vtcr_t0sz_sl0

Fields:

SL0 signed int: VTCR.SL0, starting level for stage 2 translation table walks
T0SZ signed int: VTCR.T0SZ, required input address range

ArchMsg.Warning.warning_unpredictable_write_DHCSR

Fields:

NEW unsigned int: data attempted to be written
OLD unsigned int: previous value

ArchMsg.Warning.warning_unpredictable_write_SHCSR

UNPREDICTABLE setting a pending bit to 1 for an exception with priority >= execution priority.

ArchMsg.Warning.warning_unsupported_access_to_memory_mapped_register

Access to memory mapped register is unsupported.

ArchMsg.Warning.warning_user_jmcr_access

Fields:

WRITE unsigned int: access is write

ArchMsg.Warning.warning_wcr_mask_and_bas

DBGWCR_EL1.MASK is non-zero and BAS is not 0xff.

ArchMsg.Warning.warning_wcr_mask_reserved

DBGWCR_ELn.MASK is set to a reserved value.

ArchMsg.Warning.warning_wcr_non_configuous_bas

DBGWCR_EL1.BAS has non-contiguous set of ones.

ArchMsg.Warning.warning_wvr_masked_bit_not_zero

DBGWVRn_EL1.VA contains a bit masked by DBGWCRn_EL1.MASK that is not zero.

ArchMsg.Why.why_illegal_state

An illegal mode change has occured. Fields:

MESSAGE string: The message

BRANCH_MISPREDICT

Simulating branch mispredict. Fields:

PC unsigned int: Origin address (or 0 if unavailable)

BRA_DIR

Direct branches, to immediate address. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
INST_COUNT unsigned int: The core's instruction counter, starting at 1 for the first instruction.
ISET enum: The instructions set of the branch instruction.
IS_COND bool: Indicates if this is a conditional branch.
PC unsigned int: The address of the branch instruction.
TARGET_ISET enum: The instructions set after the branch.
TARGET_PC unsigned int: The address the instruction branches to.

BRA_INDIR

Indirect branches, perhaps to a register. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
INST_COUNT unsigned int: The core's instruction counter, starting at 1 for the first instruction.
ISET enum: The instructions set of the branch instruction.
IS_COND bool: Indicates if this is a conditional branch.
PC unsigned int: The address of the branch instruction.
TARGET_ISET enum: The instructions set after the branch.
TARGET_PC unsigned int: The address the instruction branches to.

CACHE_MAINTENANCE_OP

Cache Maintenance Operation. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
DATA unsigned int: Specified MVA or Set/way
FUNCTION enum: Clean / Invalidate
SCOPE enum: Affected region
SIDE enum: Inst / Data.

CCFAIL

Conditional instruction condition check fail. Fields:

COND enum: The condition of the conditional instruction.
CORE_NUM unsigned int: Core number in a multi processor.
PC unsigned int: The address of the conditional instruction.

CCFAIL_UNC

Unconditional instruction condition check fail. Fields:

COND enum: The condition of the conditional instruction.
CORE_NUM unsigned int: Core number in a multi processor.
PC unsigned int: The address of the conditional instruction.

CCPASS

Conditional instruction condition check pass. Fields:

COND enum: The condition of the conditional instruction.
CORE_NUM unsigned int: Core number in a multi processor.
PC unsigned int: The address of the conditional instruction.

CCPASS_UNC

Unconditional instruction condition check pass. Fields:

COND enum: The condition of the conditional instruction.
CORE_NUM unsigned int: Core number in a multi processor.
PC unsigned int: The address of the conditional instruction.

CHECKPOINT_MESSAGE

Report error messages from the checkpointing process. Fields:

message string: Message contents.

CHECKPOINT_RESTORE_END

Checkpoint restore completed.

CHECKPOINT_RESTORE_START

Checkpoint restore about to start.

CHECKPOINT_SAVE_END

Checkpoint save completed.

CHECKPOINT_SAVE_START

Checkpoint save about to start.

CODE_CACHE_FLUSH

Code cache flushed.

CODE_CACHE_FULL

Code cache full.

COMPILE_BLOCK_END

Last instruction of basic block translated. Fields:

VADDR unsigned int: Address of next instruction after this basic block

COMPILE_BLOCK_START

First instruction of basic block translated. Fields:

VADDR unsigned int: Address of first instruction in basic block

COMPILE_INST

ARM instruction compiled. Fields:

DISASS string: Disassembly of the instruction.
ISET enum: The instruction set of this instruction.
ITSTATE unsigned int: The ITSTATE current for the instruction.
OPCODE unsigned int: The opcode of the instruction.
PC unsigned int: The address of the instruction.
SIZE unsigned int: The size of the instruction in bytes.

CONTEXTIDR

Context ID Register write. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
NS bool: Secure or nonsecure banked register is accessed.
UNDEF bool: The register accessed is undefined.
VALUE unsigned int: The new value written.

CORE_ENDIAN

Core BE8 Big-Endian state changed. Fields:

BE8 bool: Core BE8 Big-Endian state

CORE_INFO

Static processor attributes. Only triggered by a call to DumpState(). Fields:

ARCH_PROFILE enum: The architecture profile of the core.
CLUSTER_ID unsigned int: The cluster ID of this processor.
CORE_NUM unsigned int: The number of this core in an MP processor.
FPU_VERSION enum: The VFP version implemented by the core.
MEM_ARCH enum: The memory architecture of the core.
NUM_CORES unsigned int: The number of cores in this MP processor.
QUANTUM_SIZE unsigned int: The default quantum size of the core.
SECURITY_FEATURES bool: Does the core have security features?

CORE_LOADS

Processor load accesses. Fields:

ACQREL enum: Is this an acquire/release
ATTR unsigned int: Memory attributes [11] non-secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes, ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable
ATTR2 unsigned int: Second page memory attributes, [11] non-secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes, ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable
CURRENT_TIME unsigned int: The core's current time, as simulated time plus local time.
DATA unsigned int: The data read or written.
ELEMENT_SIZE unsigned int: Width of each element.
LOCAL_TIME unsigned int: The core's local time, relative to the current quantum.
LOCK enum: Normal, exclusive or locked access.
NSDESC unsigned int: The physical address non-secure bit.
NSDESC2 unsigned int: The second page physical address non-secure bit.
PADDR unsigned int: The physical (translated) address.
PADDR2 unsigned int: If different from PADDR, the physical address of the second page of the access.
RESPONSE enum: 0=Aborted, 1=OK, 2=Exclusive Failed
SIZE unsigned int: Width of the access in bytes. Only required if DATA is not traced.
TRANS bool: Is this a translated access.
VADDR unsigned int: The virtual address of the access.

CORE_REGS

Changes of the core registers R0 to R14. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
ID unsigned int: The register number, 0 to 14.
MODE enum: Bank of the register accessed.
OLD_VALUE unsigned int: The old value overwritten.
PHYS_ID enum: The physical register accessed.
VALUE unsigned int: The new value written to the register.

CORE_REGS64

Changes of the core registers X0..X30, SP_ELn. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
ID enum: The register number, 0..30 for X0..X30, >=32 for SP_ELn.
OLD_VALUE unsigned int: The old value overwritten.
VALUE unsigned int: The new value written to the register.

CORE_STORES

Processor store accesses. Fields:

ACQREL enum: Is this an acquire/release
ATTR unsigned int: Memory attributes [11] non-secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes, ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable
ATTR2 unsigned int: Second page memory attributes, [11] non-secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes, ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable
CURRENT_TIME unsigned int: The core's current time, as simulated time plus local time.
DATA unsigned int: The data read or written.
ELEMENT_SIZE unsigned int: Width of each element.
LOCAL_TIME unsigned int: The core's local time, relative to the current quantum.
LOCK enum: Normal, exclusive or locked access.
NSDESC unsigned int: The physical address non-secure bit.
NSDESC2 unsigned int: The second page physical address non-secure bit.
PADDR unsigned int: The physical (translated) address.
PADDR2 unsigned int: If different from PADDR, the physical address of the second page of the access.
RESPONSE enum: 0=Aborted, 1=OK, 2=Exclusive Failed
SIZE unsigned int: Width of the access in bytes. Only required if DATA is not traced.
TRANS bool: Is this a translated access.
VADDR unsigned int: The virtual address of the access.

CP14_READ

System Coprocessor register read. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
CRm unsigned int: CRm
CRn unsigned int: CRn
NS bool: Secure or nonsecure banked register is accessed.
REG_NAME string: Name of the CP14 register accessed.
UNDEF bool: The register accessed is undefined.
VALUE unsigned int: The value read.
opc1 unsigned int: opcode 1
opc2 unsigned int: opcode 2

CP14_WRITE

System Coprocessor register write. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
CRm unsigned int: CRm
CRn unsigned int: CRn
NS bool: Secure or nonsecure banked register is accessed.
REG_NAME string: Name of the CP14 register accessed.
UNDEF bool: The register accessed is undefined.
UPDATED_VALUE unsigned int: Updated value of the register now it has been written.
VALUE unsigned int: The new value written.
opc1 unsigned int: opcode 1
opc2 unsigned int: opcode 2

CP15_READ

System Coprocessor register read. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
CRm unsigned int: CRm
CRn unsigned int: CRn
NS bool: Secure or nonsecure banked register is accessed.
REG_NAME string: Name of the CP15 register accessed.
UNDEF bool: The register accessed is undefined.
VALUE unsigned int: The value read.
opc1 unsigned int: opcode 1
opc2 unsigned int: opcode 2

CP15_READ64

System Coprocessor register read. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
CRm unsigned int: CRm
NS bool: Secure or nonsecure banked register is accessed.
REG_NAME string: Name of the CP15 register accessed.
UNDEF bool: The register accessed is undefined.
VALUE unsigned int: The value read.
opc unsigned int: opcode 1

CP15_WRITE

System Control Coprocessor register write. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
CRm unsigned int: CRm
CRn unsigned int: CRn
NS bool: Secure or nonsecure banked register is accessed.
REG_NAME string: Name of the CP15 register accessed.
UNDEF bool: The register accessed is undefined.
UPDATED_VALUE unsigned int: Updated value of the register now it has been written.
VALUE unsigned int: The new value written.
opc1 unsigned int: opcode 1
opc2 unsigned int: opcode 2

CP15_WRITE64

System Coprocessor register write. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
CRm unsigned int: CRm
NS bool: Secure or nonsecure banked register is accessed.
REG_NAME string: Name of the CP15 register accessed.
UNDEF bool: The register accessed is undefined.
UPDATED_VALUE unsigned int: Updated value of the register now it has been written.
VALUE unsigned int: The new value written.
opc unsigned int: opcode 1

CPSR

CPSR change. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
OLD_VALUE unsigned int: The old CPSR value
UNKNOWN unsigned int: Bits within the register that have unknown value.
VALUE unsigned int: The new CPSR value

CRYPTO_SPEC

Every crypto instruction speculatively executed.

DEBUG_EVENT

Hardware debug support event. Fields:

EVENT enum: Description of event
VALUE unsigned int: data value

END_COMPILE

Compilation end. Fields:

END_OF_PAGE_COUNT unsigned int: Number of basic blocks exited due to page boundary since START_COMPILE.
FETCHFAIL_COUNT unsigned int: Number of basic blocks exited due to ifetch failure START_COMPILE.
INST_COUNT unsigned int: Number of instructions compiled since START_COMPILE.
NONSEQ_COUNT unsigned int: Number of basic blocks exited due to non-sequential instructions since START_COMPILE.
PAGE_STRADDLE_COUNT unsigned int: Number of basic blocks exited due to unaligned instructions crossing page since START_COMPILE.

EXCEPTION

Exception taken. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
IS_PHYSICAL bool: Physical or Virtual exception
LR unsigned int: The value assigned to the link register.
PC unsigned int: The location where the exception occurred.
PREFERRED_RETURN unsigned int: The preferred return address for the exception.
TARGET_ISET enum: The instruction set of the exception handler code.
TARGET_PC unsigned int: The address the exception branches to.
VECTOR enum: The exception vector.

EXCEPTION_END

Every exception completed.

EXCEPTION_RAISE

Every exception raised.

EXCEPTION_RETURN

Branches on leaving exception. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
INST_COUNT unsigned int: The core's instruction counter, starting at 1 for the first instruction.
ISET enum: The instructions set of the branch instruction.
IS_COND bool: Indicates if this is a conditional branch.
PC unsigned int: The address of the branch instruction.
TARGET_ISET enum: The instructions set after the branch.
TARGET_PC unsigned int: The address the instruction branches to.

EXCEPTION_START

Every exception started.

FIQ_TAKEN

FIQ taken exception.

INST

Every instruction executed. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
CURRENT_TIME unsigned int: The core's current time, as simulated time plus local time.
DISASS string: Disassembly of instruction.
INST_COUNT unsigned int: The core's instruction counter, starting at 1 for the first instruction.
ISET enum: The current instruction set.
ITSTATE unsigned int: The current ITSTATE.
LOCAL_TIME unsigned int: The core's local time, relative to the current quantum.
MODE enum: The mode the core is in.
NS unsigned int: The core's non-secure bit.
NSDESC unsigned int: The physical address non-secure bit.
NSDESC2 unsigned int: The second page physical address non-secure bit.
OPCODE unsigned int: The opcode of the instruction.
PADDR unsigned int: The physical address of the instruction.
PADDR2 unsigned int: If different from PADDR, the physical address of the second page of the instruction.
PC unsigned int: The address of the instruction.
SIZE unsigned int: The size of the instruction in bytes.

INST_END

Every instruction completed.

INST_START

Every instruction started. Fields:

ISET enum: The current instruction set.
MODE enum: The mode the core is in.
NS enum: The current Secure State.
PC unsigned int: The address of the conditional instruction.

IRQ_TAKEN

IRQ taken exception.

LOCAL_MONITOR

Local monitor activity. Fields:

PADDR unsigned int: Local Monitor Address
State enum: State of the monitor (Open/Exclusive)

MEMMAP_DEBUG_READ

Memory mapped reads to the debug registers. Fields:

ADDR unsigned int: address
CORE_NUM unsigned int: Core number in a multi processor.
EXT bool: Whether access is from an external device (such as the DAP)
REG_NAME string: Name of the debug register accessed.
UNDEF bool: The register accessed is undefined.
VALUE unsigned int: The value read.

MEMMAP_DEBUG_WRITE

Memory mapped writes to the debug registers. Fields:

ADDR unsigned int: address
CORE_NUM unsigned int: Core number in a multi processor.
EXT bool: Whether access is from an external device (such as the DAP)
REG_NAME string: Name of the debug register accessed.
UNDEF bool: The register accessed is undefined.
VALUE unsigned int: The new value written.

MMU_TRANS

Address translation information. Fields:

ASID unsigned int: Address space identifier.
CORE_NUM unsigned int: Core number in a multi processor.
Hyp bool: Entry matches in Hyp state only
INNERCACHE_RA bool: Is the inner cache allocate on read
INNERCACHE_TRANSIENT bool: Is the inner write-through transient
INNERCACHE_TYPE enum: Inner Caching scheme (NC/MB/WA).
INNERCACHE_WA bool: Is the inner cache allocate on write
MEMTYPE enum: Memory type.
NSDESC enum: Is secure side supposed to access secure or nonsecure memory
OUTERCACHE_RA bool: Is the outer cache allocate on read
OUTERCACHE_TRANSIENT bool: Is the outer write-through transient
OUTERCACHE_TYPE enum: Outer Caching scheme (NC/MB/WA).
OUTERCACHE_WA bool: Is the outer cache allocate on write
PADDR unsigned int: Physical address of the access.
PAGESIZE unsigned int: Page size as log2(size).
SH enum: Shareability
SIDE enum: Inst / Data.
VADDR unsigned int: Virtual address of the access.
VMID unsigned int: Virtual machine identifier.
nG enum: Flag indicating whether ASID will be matched

MMU_TTB_READ

This event is triggered by reads caused by a translation table walk. Fields:

ABORTED bool: Was the walk successful.
DATA unsigned int: The data read.
IPA unsigned int: For stage 1, the IPA of the read.
LEVEL unsigned int: Translation table level
LPAE bool: Is this for an LPAE translation
NSmem bool: Non secure memory access
NSreq bool: Non secure request
PADDR unsigned int: The physical address of the read.
SIDE enum: Inst / Data.
STAGE unsigned int: Translation stage

MMU_TTB_WRITE

This event is triggered by writes caused by a translation table walk. Fields:

ABORTED bool: Was the walk successful.
DATA unsigned int: The data written.
IPA unsigned int: For stage 1, the IPA of the write.
LEVEL unsigned int: Translation table level
LPAE bool: Is this for an LPAE translation
NSmem bool: Non secure memory access
NSreq bool: Non secure request
PADDR unsigned int: The physical address of the write.
SIDE enum: Inst / Data.
STAGE unsigned int: Translation stage

MODE_CHANGE

Mode change. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
MODE enum: The new mode.
NON_SECURE enum: The new security state
OLD_MODE enum: The old mode.

PERIODIC

Called for every quantum. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
INST_COUNT unsigned int: The instruction count of this CPU.
PC unsigned int: The address of the next instruction to be executed on this CPU.

PMU_COUNTER_OVERFLOW

PMU counter overflow. Fields:

EVENT_ID unsigned int: Event Identifier
INDEX unsigned int: Counter index (as selected by PMSELR).
INTERRUPT bool: Is interrupt enabled on overflow for this counter

PREFETCH_MEMORY64

Prefetch from PRFM or PRFUM instructions. Fields:

PRFOP unsigned int: Prefetch hint
VADDR unsigned int: Virtual address of the location that should be prefetched.

PRELOAD_DATA

Data preload from PLD instruction. Fields:

VADDR unsigned int: Virtual address of the data that should be preloaded.

PRELOAD_INST

Instruction preload from PLI instruction. Fields:

VADDR unsigned int: Virtual address of the instruction that should be preloaded.

PRE_CORE_LOAD

Trace just before a core load. Fields:

CURRENT_TIME unsigned int: The core's current time, as simulated time plus local time.
LOCAL_TIME unsigned int: The core's local time, relative to the current quantum.

PRE_CORE_STORE

Trace just before a core store. Fields:

CURRENT_TIME unsigned int: The core's current time, as simulated time plus local time.
LOCAL_TIME unsigned int: The core's local time, relative to the current quantum.

PRE_TTB_READ

This event is triggered before reads caused by a translation table walk. Fields:

ADDR unsigned int: The physical address of the read.

RUN_STATE

Run state transition. Fields:

INST_COUNT unsigned int: Ticks count at point of transition.
NEW enum: New run state.
OLD enum: Old run state.

SEMIHOSTING_CALL

Call of a semihost function occurred. Fields:

PC unsigned int: The program counter after the semihosting call.

SEMIHOSTING_PRECALL

About to call semihost. Fields:

NS bool: Is Non-Secure.
REG_WIDTH unsigned int: The current register width in bytes.

SIGNAL

External signal state change. Fields:

SIGNAL enum: Signal that changed
STATE bool: Signal asserted state

SOFTWARE_STEP

Return the Debug Software Step state. Fields:

STATE enum: Software Step state

SPSR

SPSR change. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
MODE enum: Which of the banked SPSR registers is written.
OLD_VALUE unsigned int: The old SPSR value
VALUE unsigned int: The new SPSR value

START_COMPILE

Compilation started. Fields:

VADDR unsigned int: Instruction where compilation begins.

SYNC

Called for every synchronization. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
INST_COUNT unsigned int: The instruction count of this CPU.
LOCAL_QUANTUM unsigned int: The local quantum of this CPU.
LOCAL_TIME unsigned int: The local time of this CPU.

SYSCALL

System call instruction executed. Fields:

IMM unsigned int: Immediate value of the system call instruction.
TYPE enum: System call type.
VADDR unsigned int: Instruction that caused the system call.

SYSREG_READ64

System Coprocessor register read. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
REGNUM enum: Internal register number
UNDEF bool: The register accessed is undefined.
VALUE unsigned int: The value read.

SYSREG_UPDATE32

Triggers when the system updates a register. Fields:

REG enum: Register number.
UNKNOWN unsigned int: Bits of the register which became unknown.
VALUE unsigned int: Value written to the register.

SYSREG_UPDATE64

Triggers when the system updates a register. Fields:

REG enum: Register number.
UNKNOWN unsigned int: Bits of the register which became unknown.
VALUE unsigned int: Value written to the register.

SYSREG_WRITE64

System Coprocessor register write. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
REGNUM enum: Internal register number
UNDEF bool: The register accessed is undefined.
UPDATED_VALUE unsigned int: Updated value of the register now it has been written.
VALUE unsigned int: The new value written.

UNALIGNED_LDST_RETIRED

Processor unaligned load/store. Fields:

ACCESS_SIZE unsigned int: Log2 of the access width in bytes used for alignment checking (1=>half-word, 2->word ...)
NUMBER_OF_BEATS unsigned int: Number of accesses (beats) in this burst (Total size in bytes is ACCESS_SIZE * NUMBER_OF_BEATS)
VADDR unsigned int: The virtual address of the access

VFP_D_REGS

VFP/NEON D 64 bit register write. Fields:

ALIASING enum: Type of register aliasing used
CORE_NUM unsigned int: Core number in a multi processor.
ID unsigned int: The register number.
MASK unsigned int: Mask for partial register update.
OLD_VALUE unsigned int: The old value overwritten.
VALUE unsigned int: The new value written to the register.

VFP_Q_REGS

VFP/NEON Q 128 bit register write. Fields:

ALIASING enum: Type of register aliasing used
CORE_NUM unsigned int: Core number in a multi processor.
ID unsigned int: The register number.
MASK unsigned int: Mask for partial register update.
OLD_VALUE unsigned int: The old value overwritten.
VALUE unsigned int: The new value written to the register.

VFP_SYS_REGS

Writes to the VFP/NEON units system registers. Fields:

CORE_NUM unsigned int: Core number in a multi processor.
ID enum: Which VFP system register is written.
OLD_VALUE unsigned int: The register's old value overwritten.
VALUE unsigned int: The new value written to the VFP system register.

VFP_S_REGS

VFP/NEON S 32 bit register write. Fields:

ALIASING enum: Type of register aliasing used.
CORE_NUM unsigned int: Core number in a multi processor.
ID unsigned int: The register number.
OLD_VALUE unsigned int: The old value overwritten.
VALUE unsigned int: The new value written to the register.

WFE_END

WFE ended. Fields:

INST_COUNT unsigned int: Ticks count when leaving WFE.

WFE_EVENT_REGISTER

WFE event register status: set/clear, reason. Fields:

INST_COUNT unsigned int: Ticks count.
REASON enum: Reason for set/clear. Only REASON==0 (Cleared by WFE) clears the bit, all other reasons set it.

WFE_IGNORED

WFE ignored. Fields:

EVENT bool: This WFE was ignored because the event register was set.
INST_COUNT unsigned int: Ticks count when ignoring WFE.
TRAPPED bool: This WFE was trapped.

WFE_START

WFE entered. Fields:

INST_COUNT unsigned int: Ticks count when entering WFE.

WFI_END

WFI ended. Fields:

INST_COUNT unsigned int: Ticks count when leaving WFI.

WFI_IGNORED

WFI ignored. Fields:

DISABLED bool: This WFI was ignored because WFI is disabled.
INST_COUNT unsigned int: Ticks count when ignoring WFI.
REASON enum: specifies reason why WFI trace was ignored
TRAPPED bool: This WFI was trapped.

WFI_START

WFI entered. Fields:

INST_COUNT unsigned int: Ticks count when entering WFI.

WFI_WAKEUP

WFI wakeup. Fields:

INST_COUNT unsigned int: Ticks count when WFI wakeup occurred.
REASON enum: Reason for wakeup.

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