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PVBusLogger - trace

This section describes the trace sources.

READ_ACCESS

Trace access at this point in the PVBus hierarchy. Fields:

ACCESS_SIZE unsigned int
Log2 of access size (i.e. 0=byte, 1=halfword, 2=word, 3=doubleword ...)
ACE enum
Encodes the ACE operation
ATTR unsigned int
Transaction Attributes: [12] instruction fetch [11] non_secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable). All other bits are implementation defined
DATA unsigned int
The data transferred
LATENCY unsigned int
Time downstream (ticks)
MASTER_ID unsigned int
The AXI Master ID
NUMBER_OF_BEATS unsigned int
The number of data transfers (beats) in this burst
PADDR unsigned int
Physical address of access
RESPONSE enum
Whether the transaction was successful, or an error occurred
USER_FLAGS unsigned int
Core specific additional signals

READ_ACCESS_START

Trace access at this point in the PVBus hierarchy. Fields:

ACCESS_SIZE unsigned int
Log2 of access size (i.e. 0=byte, 1=halfword, 2=word, 3=doubleword ...)
ACE enum
Encodes the ACE operation
ATTR unsigned int
Transaction Attributes: [12] instruction fetch [11] non_secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable). All other bits are implementation defined
DATA unsigned int
The data transferred
MASTER_ID unsigned int
The AXI Master ID
NUMBER_OF_BEATS unsigned int
The number of data transfers (beats) in this burst
PADDR unsigned int
Physical address of access
USER_FLAGS unsigned int
Core specific additional signals

WRITE_ACCESS

Trace access at this point in the PVBus hierarchy. Fields:

ACCESS_SIZE unsigned int
Log2 of access size (i.e. 0=byte, 1=halfword, 2=word, 3=doubleword ...)
ACE enum
Encodes the ACE operation
ATTR unsigned int
Transaction Attributes: [12] instruction fetch [11] non_secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable). All other bits are implementation defined
DATA unsigned int
The data transferred
LATENCY unsigned int
Time downstream (ticks)
MASTER_ID unsigned int
The AXI Master ID
NUMBER_OF_BEATS unsigned int
The number of data transfers (beats) in this burst
PADDR unsigned int
Physical address of access
RESPONSE enum
Whether the transaction was successful, or an error occurred
USER_FLAGS unsigned int
Core specific additional signals

WRITE_ACCESS_START

Trace access at this point in the PVBus hierarchy. Fields:

ACCESS_SIZE unsigned int
Log2 of access size (i.e. 0=byte, 1=halfword, 2=word, 3=doubleword ...)
ACE enum
Encodes the ACE operation
ATTR unsigned int
Transaction Attributes: [12] instruction fetch [11] non_secure, [10] privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer cacheable attributes, [3:0] inner cacheable attributes ([7]/[3] write allocate, [6]/[2] hittable, [5]/[1] cacheable, [4]/[0] bufferable). All other bits are implementation defined
DATA unsigned int
The data transferred
MASTER_ID unsigned int
The AXI Master ID
NUMBER_OF_BEATS unsigned int
The number of data transfers (beats) in this burst
PADDR unsigned int
Physical address of access
USER_FLAGS unsigned int
Core specific additional signals
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