The intention of this section is to standardize architecture names, for example for use in compiler command lines. Toolchains should accept these names case-insensitively where possible, or use all lowercase where not possible. Tools may apply local conventions such as using hyphens instead of underscores.
(Note: processor names, including from the Arm Cortex® processor family, are used as illustrative examples. This specification is applicable to any processors implementing the Arm architecture.)
The recommended CPU architecture names are as specified under
Tag_CPU_arch in [BA]. For details of how to use predefined macros to
test architecture in source code, see A32/T32 instruction set architecture.
The following table lists the architectures and the A32 and T32 instruction set versions.
Note that there is some architectural variation that is not visible through ACLE; either because it is only relevant at the system level (for example the Large Physical Address Extension) or because it would be handled by the compiler (for example hardware divide might or might not be present in the Armv7-A architecture).
For details of how to test FPU features in source code, see Floating-point, Advanced SIMD (Neon) and MVE hardware. In particular, for testing which precisions are supported in hardware, see _ssec-HWFP.
||VFPv3 with FP16||Cortex-A9 (with Neon)|
||VFPv3 with 16 D-registers||Cortex-R4F|
||VFPv3 with 16 D-registers and FP16||Cortex-A9 (without Neon), Cortex-R7|
||VFPv3 with 16 D-registers, single-precision only||Cortex-R5 with SP-only|
||VFPv4 (including FMA and FP16)||Cortex-A15|
||VFPv4 (including FMA and FP16) with 16 D-registers||Cortex-A5 (VFP option)|
||FPv4 with single-precision only||Cortex-M4.fp|