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CTRL

Control register for initiating Flash accesses.

The CTRL register characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsThere is only one configuration.
Attributes
Offset0x014
TypeRead‑write
Reset0x0
Width32

The following figure shows the bit assignments.

Figure 3-11 CTRL register bit assignments


The following list shows the register bit assignments.

[4] ABORT
Abort currently ongoing command that is initiated towards the embedded Flash from the APB interface. When ABORT is written, the CMD field is ignored. ABORT is effective only when STATUS.CMD_ACCEPT is set. Reading back ABORT field shows the status of the GFB interface fabort signal.
[2:0] CMD

Initiate a command to the embedded Flash for the address that is stored in the ADDR register and with the data that are stored in DATA0 register. For WRITE and ROW WRITE commands, software must ensure that the state of the addressed word is cleared. The commands are:

0b001: READ

0b010: WRITE

0b011: ROW WRITE

0b100: ERASE

0b111: MASS ERASE

0b000: Reserved

0b101: Reserved

0b110: Reserved

Writing reserved commands has no effect. Reading back the CMD value shows the currently pending CMD. When the CMD is accepted, the CMD field is cleared to 0b000.

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