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IRQ_STATUS_CLR
Interrupt status clear register for acknowledging different interrupt sources.
The IRQ_STATUS_CLR register characteristics are:
| Usage constraints | There are no usage constraints. | ||||||||
| Configurations | There is only one configuration. | ||||||||
| Attributes |
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The following figure shows the bit assignments.
Figure 3-9 IRQ_STATUS_CLR register bit assignments
The following list shows the register bit assignments.
- [4] READ_OVERFLOW_IRQ_STS_CLR
- Clears the status of the READ_OVERFLOW_IRQ bit. Write to 1 clears the interrupt. Write to 0 has no effect. Reading this bit shows the current status of the interrupt bit.
- [3] CMD_REJECT_IRQ_STS_CLR
- Clears the status of the CMD_REJECT_IRQ bit. Write to 1 clears the interrupt. Write to 0 has no effect. Reading this bit shows the current status of the interrupt bit.
- [2] CMD_FAIL_IRQ_STS_CLR
- Clears the status of the CMD_FAIL_IRQ bit. Write to 1 clears the interrupt. Write to 0 has no effect. Reading this bit shows the current status of the interrupt bit.
- [1] CMD_SUCCESS_IRQ_STS_CLR
- Clears the status of the CMD_SUCCESS_IRQ bit. Write to 1 clears the interrupt. Write to 0 has no effect. Reading this bit shows the current status of the interrupt bit.
- [0] CMD_ACCEPT_IRQ_STS_CLR
- Clears the status of the CMD_ACCEPT_IRQ bit. Write to 1 clears the interrupt. Write to 0 has no effect. Reading this bit shows the current status of the interrupt bit.