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STATUS

Status register for showing the state of the embedded Flash accesses.

The STATUS register characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsThere is only one configuration.
Attributes
Offset0x018
TypeRead‑only
Reset0x0
Width32

The following figure shows the bit assignments.

Figure 3-12 STATUS register bit assignments


The following list shows the register bit assignments.

[5] ARBITRATION_LOCKED
When this bit reads 1, it means that the other interface keeps the arbitration in locked state and no APB commands are serviced until the locked state is removed. Software can use this bit to detect why the APB request is being held up.
[4] CMD_FINISH
When this bit reads 1, it means that the previously accepted command is finished but the result cannot be updated in the STATUS register because the interrupt bits are still set. When the result interrupt bits are cleared, the status can be updated and this bit is automatically cleared.
[3] CMD_FAIL
When this bit reads 1, it means that the previously accepted command has finished with a failure. Either this bit or the CMD_SUCCESS bit is set for the finished command. Updated when CMD_SUCCESS_IRQ or CMD_FAIL_IRQ is set. Valid until the CMD_SUCCESS_IRQ or CMD_FAIL_IRQ bit is cleared.
[2] CMD_SUCCESS
When this bit reads 1, it means that the previously accepted command has finished successfully. Either this bit or the CMD_FAIL bit is set for the finished command. Updated when CMD_SUCCESS_IRQ or CMD_FAIL_IRQ is set. Valid until the CMD_SUCCESS_IRQ or CMD_FAIL_IRQ bit is cleared.
[1] CMD_ACCEPT
Selecting CMD_PENDING to be executed towards the embedded Flash sets this bit to 1 and means that the command is being forwarded to the embedded Flash. Set to 1 when the CMD_PENDING bit is cleared. Cleared when the command has finished and the CMD_SUCCESS_IRQ or CMD_FAIL_IRQ status bits are cleared for the previous transfer. If the status results of the previous command are not cleared, the command might still be finished for the embedded Flash, but the results cannot update until the previous results are cleared. If an already pending command is accepted when the current command has finished, this bit stays asserted.
[0] CMD_PENDING
When the CTRL register is written, the command goes into the arbitration queue and waits to be arbitrated towards the embedded Flash. This bit is set when the command is initiated, but still pending in the queue, and is cleared when the embedded Flash arbitrates and accepts the command. This bit is also set when ABORT is written to the CTRL register, and is cleared when the aborted command has finished.
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