Generic Flash Bus
The Generic Flash Bus enables GFC-100 to access embedded Flash.
Commands are received from the system through the AHB‑Lite and APB slave interfaces, and converted internally to transfers over the GFB. A process‑specific part that is connected to the GFB is expected to serve as a slave while GFC-100 is the master.
GFC-100 supports all commands that are specified in the Arm® AMBA® Generic Flash Bus Protocol Specification.
The GFB allows access to a 4MB memory area. The address MSB allows access to an extended region that might be present in the Flash macro. Depending on how the process‑specific part handles addresses, the MSB separates the 4MB memory into two halves so that a 2MB main memory and an extended region can be supported. The extended region is assumed to be smaller than 2MB, and therefore, faddr is sufficient to access the entire extended region.
The GFB supports a fixed read data width of 128 bits, that matches the data width of the AHB‑Lite slave interface. Write data is sent over a 32‑bit fwdata bus. A full width data write of 128 bits is sent over the GFB as four separate writes. Bits faddr[3:2] select the location of the 32‑bit write data within the 128‑bit data word in little‑endian order.
GFC-100 is the GFB master and drives commands over the GFB. A GFB slave is allowed to delay its response to commands. The process‑specific part can take several cycles to respond to READ commands. However, WRITE and ERASE commands can take many more cycles to execute.
Failed transactions can generate a 2‑cycle error response from the process‑specific part.
The fabort signal can abort commands that the GFB master initiates. The signal is driven from the APB registers. The method that the process‑specific part uses to support the abort function depends on its implementation.
- Commands from the AHB‑Lite slave interface cannot be aborted.
- For more information about GFB transactions, see the Arm® AMBA® Generic Flash Bus Protocol Specification.