Generic Flash Bus signals
The GFB interface processes several input and output signals.
The following table shows the GFB signals.
Table A-4 Generic Flash Bus signals
|Signal name||Direction||Source or destination||Description|
Address width is fixed at 22 bits to allow accesses to a 4MB embedded Flash that can be divided into a 2MB main memory and extended memory.
faddr selects between main and extended regions:
0 = Main area.
1 = Extended area.
faddr[3:2] selects the location of the 32‑bit write data within the 128‑bit interface:
faddr[1:0] is not used because the minimum data width is 32 bits.
When HIGH, the master requests to abort the command that is running.
|fwdata[31:0]||Output||Process‑specific part||32‑bit write data bus.|
|frdata[127:0]||Input||Process‑specific part||128‑bit read data bus.|
Command ready indication.
Driven LOW if the process‑specific part requires wait states to complete the access.
Driven HIGH when the process‑specific part is ready with the previous access and is able to accept a new command.
Flash error indication for the previously accepted command.
Driven HIGH for two cycles when an error is indicated for the command that is running.
- GFB signals that are not shown in the table are not used in GFC-100.
- The GFC-100 and the GFB slave logic inside the process‑specific part are expected to be in the same power domain. Therefore, the GFB does not require isolation values.